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| 型號(hào)： | ADUM3100 |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 英文描述： | Digital Isolator, Enhanced System-Level ESD Reliability |
| 中文描述： | 數(shù)字隔離器，提高其系統(tǒng)級(jí)靜電放電的可靠性 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 289K |
| 代理商： | ADUM3100 |
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ADuM3100
ELECTRICAL SPECIFICATIONS, MIXED 5 V/3 V OR 3 V/5 V OPERATION
1
5 V/3 V operation: 4.5 V ≤ V
DD1
≤ 5.5 V, 3.0 V ≤ V
DD2
≤ 3.6 V. 3 V/5 V operation: 3.0 V ≤ V
DD1
≤ 3.6 V, 4.5 V ≤ V
DD2
≤ 5.5 V. All
minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications
are at T
A
= 25°C, V
DD1
= 3.3 V, V
DD2
= 5 V or V
DD1
= 5 V, V
DD2
= 3.3 V.
Table 3.
Parameter
Symbol
Min
DC SPECIFICATIONS
Input Supply Current, Quiescent
I
DDI (Q)
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current
2
, Quiescent
I
DDO (Q)
5 V/3 V Operation
3 V/5 V Operation
Input Supply Current, 25 Mbps
I
DDI (25)
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current
2
, 25 Mbps
I
DDO (25)
5 V/3 V Operation
3 V/5 V Operation
Input Supply Current, 50 Mbps
I
DDI (50)
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current
2
, 50 Mbps
I
DDO (50)
5 V/3 V Operation
3 V/5 V Operation
Input Currents
I
IA
–10
Rev. A | Page 5 of 16
Typ
1.3
0.7
0.1
0.15
3.2
2.6
0.4
0.6
5.5
4.6
0.7
1.1
+0.01
Max
1.8
0.9
0.2
0.25
4.5
3.4
0.8
1.1
8.0
6.6
1.7
1.6
+10
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
Test Conditions
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
25 MHz logic signal freq.
25 MHz logic signal freq.
25 MHz logic signal freq.
25 MHz logic signal freq.
0 ≤ V
IA
, V
IB
, V
IC
, V
ID
≤
V
DD1
or V
DD2
I
O
= –20 μA, V
I
= V
IH
I
O
= –2.5 mA, V
I
= V
IH
I
O
= 20 μA, V
I
= V
IL
I
O
= 400 μA, V
I
= V
IL
I
O
= 2.5 mA, V
I
= V
IL
I
O
= –20 μA, V
I
= V
IH
I
O
= –4 mA, V
I
= V
IH
I
O
= 20 μA, V
I
= V
IL
I
O
= 400 μA, V
I
= V
IL
I
O
= 4 mA, V
I
= V
IL
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
Logic High Output Voltage, 5 V/3 V Operation
Logic Low Output Voltage, 5 V/3 V Operation
V
OH
V
OL
V
OH
V
OL
PW
PW
t
PHL,
t
PLH
V
DD2
– 0.1
V
DD2
– 0.5
V
DD2
– 0.1
V
DD2
– 0.8
25
50
3.3
3.0
0.0
0.04
0.3
5.0
4.6
0.0
0.03
0.3
0.1
0.1
0.4
0.1
0.1
0.8
40
20
V
V
V
V
V
V
V
V
V
V
ns
Mbps
ns
Mbps
Logic High Output Voltage, 3 V/5 V Operation
Logic Low Output Voltage, 3 V/5 V Operation
SWITCHING SPECIFICATIONS
For ADuM3100AR
Minimum Pulse Width
3
Maximum Data Rate
4
For ADuM3100BR
Minimum Pulse Width
3
Maximum Data Rate
4
For All Grades
Propagation Delay Time to Logic Low/
High Output
5, 6
5 V/3 V Operation (See Figure 8)
3 V/5 V Operation (See Figure 9)
Pulse-Width Distortion, |t
PLH
t
PHL
|
6
5 V/3 V Operation
3 V/5 V Operation
PWD
13
16
0.5
0.5
21
26
2
3
ns
ns
ns
ns
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
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