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參數資料
型號: ADUM3401BRWZ
廠商: ANALOG DEVICES INC
元件分類: 模擬信號調理
英文描述: Quad-Channel, Digital Isolators, Enhanced System-Level ESD Reliability
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO16
封裝: ROHS COMPLIANT, MS-013AA, SOIC-16
文件頁數: 7/24頁
文件大小: 243K
代理商: ADUM3401BRWZ
ADuM3400/ADuM3401/ADuM3402
Parameter
ADuM340xBRW
Minimum Pulse Width
3
Maximum Data Rate
4
Propagation Delay
5
Pulse-Width Distortion, |t
PLH
t
PHL
|
5
Change vs. Temperature
Propagation Delay Skew
6
Channel-to-Channel Matching,
Codirectional Channels
7
Channel-to-Channel Matching,
Opposing-Directional Channels
7
ADuM340xCRW
Minimum Pulse Width
3
Maximum Data Rate
4
Propagation Delay
5
Pulse-Width Distortion, |t
PLH
t
PHL
|
5
Change vs. Temperature
Propagation Delay Skew
6
Channel-to-Channel Matching,
Codirectional Channels
7
Channel-to-Channel Matching,
Opposing-Directional Channels
7
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance-to-High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output
8
Common-Mode Transient Immunity
at Logic Low Output
8
Refresh Rate
Input Dynamic Supply Current per Channel
9
Output Dynamic Supply Current per Channel
9
1
All voltages are relative to their respective ground.
2
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total V
DD1
and V
DD2
supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
5
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
6
t
PSK
is the magnitude of the worst-case difference in t
PHL
or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. 0 | Page 7 of 24
Symbol
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
Min
10
20
Typ
38
5
Max Unit
100
50
3
22
3
Test Conditions
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
ns
Mbps
ns
ns
ps/°C
ns
ns
t
PSKOD
6
ns
C
L
= 15 pF, CMOS signal levels
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
90
20
8.3
120
34
0.5
3
11.1 ns
45
2
16
2
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
Mbps
ns
ns
ps/°C
ns
ns
t
PSKOD
5
ns
C
L
= 15 pF, CMOS signal levels
t
PHZ
, t
PLH
6
8
ns
C
L
= 15 pF, CMOS signal levels
t
PZH
, t
PZL
6
8
ns
C
L
= 15 pF, CMOS signal levels
t
R
/t
F
|CM
H
|
25
3
35
ns
kV/μs
C
L
= 15 pF, CMOS signal levels
V
Ix
= V
DD1
/V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
mA/Mbps
mA/Mbps
|CM
L
|
25
35
kV/μs
f
r
I
DDI (D)
I
DDO (D)
1.1
0.10
0.03
Mbps
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相關代理商/技術參數
參數描述
ADUM3401BRWZ-RL 功能描述:IC DIGITAL ISOLATOR QUAD 16-SOIC RoHS:是 類別:隔離器 >> 數字隔離器 系列:iCoupler® 產品培訓模塊:IsoLoop® Isolator 標準包裝:50 系列:IsoLoop® 輸入 - 1 側/2 側:5/0 通道數:5 電源電壓:3 V ~ 5.5 V 電壓 - 隔離:2500Vrms 數據速率:110Mbps 傳輸延遲:12ns 輸出類型:CMOS 封裝/外殼:16-SOIC(0.154",3.90mm 寬) 供應商設備封裝:16-SOIC N 包裝:管件 工作溫度:-40°C ~ 85°C 其它名稱:390-1053-5
ADUM3401CRWZ 功能描述:IC DIGITAL ISOLATOR 4CH 16-SOIC RoHS:是 類別:隔離器 >> 數字隔離器 系列:iCoupler® 標準包裝:66 系列:iCoupler® 輸入 - 1 側/2 側:2/2 通道數:4 電源電壓:3.3V,5V 電壓 - 隔離:2500Vrms 數據速率:25Mbps 傳輸延遲:60ns 輸出類型:邏輯 封裝/外殼:20-SSOP(0.209",5.30mm 寬) 供應商設備封裝:20-SSOP 包裝:管件 工作溫度:-40°C ~ 105°C
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ADUM3401TRWZ-EP 功能描述:General Purpose Digital Isolator 2500Vrms 4 Channel 10Mbps 25kV/μs CMTI 16-SOIC (0.295", 7.50mm Width) 制造商:analog devices inc. 系列:iCoupler? 包裝:管件 零件狀態:有效 技術:磁耦合 類型:通用 隔離式電源:無 通道數:4 輸入 - 輸入側 1/輸入側 2:3/1 通道類型:單向 電壓 - 隔離:2500Vrms 共模瞬態抗擾度(最小值):25kV/μs 數據速率:10Mbps 傳播延遲 tpLH / tpHL(最大值):50ns,50ns 脈寬失真(最大):3ns 上升/下降時間(典型值):2.5ns,2.5ns 電壓 - 電源:3.135 V ~ 5.5 V 工作溫度:-55°C ~ 125°C 封裝/外殼:16-SOIC(0.295",7.50mm 寬) 供應商器件封裝:16-SOIC 標準包裝:47
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