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參數資料
| 型號： | ADV202BBC-150 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Circular Connector; No. of Contacts:22; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:13-35 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA144 |
| 封裝： | 13 X 13 MM, MO-192-AAD-1, CSPBGA-144 |
| 文件頁數： | 23/40頁 |
| 文件大?。?/td> | 841K |
| 代理商： | ADV202BBC-150 |
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ADV202
Rev. 0 | Page 23 of 40
Mnemonic
HOLD
Pins
Used
121-Pin
Package
144-Pin
Package
I/O
I
Description
External Hold Indication for JDATA Input/Output Stream. Polarity is
programmable in the EDMOD0 register. This pin is always an input.
Used in DCS-DMA Mode. Chip select for the FIFO assigned to
Channel 0 (asynchronous mode).
Data Request for External DMA Interface. Indicates that the ADV202
is ready to send/receive data to/from the FIFO assigned to DMA
Channel 1.
Used in DCS-DMA Mode. Service request from the FIFO assigned to
Channel 1 (asynchronous mode).
Boot Mode Configuration. This pin is read on reset to determine the
boot configuration of the on-board processor. The pin should be tied
to IOVDD or DGND through a 10 k resistor.
Data Acknowledge for External DMA Interface. Signal from the host
CPU, which indicates that the data transfer request (DREQ1) has been
acknowledged and data transfer can proceed. This pin must be held
high at all times unless a DMA or JDATA access is occurring. This pin
must be held high at all times, if the DMA interface is not used, even if
the DMA channels are disabled.
Used in DCS-DMA Mode. Chip select for the FIFO assigned to
Channel 1 (asynchronous mode).
Host Expansion Bus.
JDATA Bus (JDATA Mode).
Host Expansion Bus.
JDATA Bus (JDATA Mode).
Video Data Expansion Bus.
Host Expansion Bus.
FCS0
I
DREQ1
1
F10
F10
O
FSRQ1
O
CFG<2>
I
DACK1
1
G9
F9
I
FCS1
I
HDATA<31:28> 4
JDATA<7:4>
HDATA<27:24> 4
JDATA<3:0>
VDATA<23:20>
HDATA<23:16> 8
J2–J4, H1
H2–H4, G4
G3, G2, F4, F3,
F2 E2, E3, E4
K3, J1–J3
J4, H1–H3
H4, G1–G4,
F1–F3
I/O
I/O
I/O
I/O
I/O
I/O
VDATA<19:12>
I/O
Video Data Expansion Bus. Extended pixel interface mode. Used for
video formats that use Y and CrCb on separate buses.
When not used, this pin should be tied low.
When not used, this pin should be tied low.
This pin must be used in multiple chip mode to align the outputs of
two or more ADV202s. For details, see the Applications section and
the
ADV202 Multichip Application
application note. When not used,
this pin should be tied low.
LCODE Output in Encode Mode. When LCODE is enabled, the output
on this pin indicates on a high transition that the last data-word for a
field has been read from the FIFO. For an 8-bit interface, such as
JDATA, LCODE is asserted for four consecutive bytes and is enabled
by default.
SPI interface: S_CSEL. When not used, this pin should be tied low.
Used only with boot mode 6.
SPI interface: S_MO. When not used, this pin should be tied low.
Used only with boot mode 6.
SPI interface: S_MI. When not used, this pin should be tied low.
Used only with boot mode 6.
SPI interface: S_CLK. When not used, this pin should be tied low.
Used only with boot mode 6.
Video Data Clock. Must be supplied, if video data is input/output on
the VDATA bus.
Video Data. Unused pins should be pulled down via a 10 k resistor.
SCOMM<7>
SCOMM<6>
SCOMM<5>
8
L2
L3
L4
M2
M3
M4
I/O
I/O
I/O
SCOMM<4>
K1
L1
O
SCOMM<3>
K2
L2
O
SCOMM<2>
L5
L3
O
SCOMM<1>
K4
K1
I
SCOMM<0>
K3
K2
O
VCLK
1
E9
E12
I
VDATA<11:0>
12
D11, D10, C7,
C9, C10, B7,
B8, B9, B11,
B10, A7, A10
D10–D12,
C10–C12,
B10–B12,
A9–A11
I/O
相關PDF資料 |
PDF描述 |
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| ADV202BBCZ-115 | Circular Connector; No. of Contacts:22; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV202BBCZ-115 | 功能描述:IC VIDEO CODEC JPEG2000 121-BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數據接口:串行 分辨率（位）:18 b ADC / DAC 數量:2 / 2 三角積分調變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADV202BBCZ-135 | 功能描述:IC CODEC VIDEO 135MHZ 144CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數據接口:串行 分辨率（位）:18 b ADC / DAC 數量:2 / 2 三角積分調變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADV202BBCZ-150 | 功能描述:IC VIDEO CODEC JPEG2000 144CSBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數據接口:串行 分辨率（位）:18 b ADC / DAC 數量:2 / 2 三角積分調變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADV202BBCZ-157 | 制造商:Analog Devices 功能描述: |
| ADV202BBCZRL-115 | 功能描述:IC CODEC VIDEO 115MHZ 121CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數據接口:串行 分辨率（位）:18 b ADC / DAC 數量:2 / 2 三角積分調變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
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