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參數(shù)資料
| 型號： | ADV3003ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 0K |
| 描述： | IC EQUALZR HDMI/DVI TMDS 40LFCSP |
| 標準包裝： | 750 |
| 應用： | DVI，HDMI 均衡器/驅(qū)動器 |
| 接口： | TMDS |
| 電源電壓： | 3 V ~ 3.6 V |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
HDMI/DVI TMDS Equalizer
ADV3003
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2008 Analog Devices, Inc. All rights reserved.
FEATURES
One input, one output HDMI/DVI high speed signal
equalizer/driver
Enables HDMI 1.3 receive-compliant input
Four TMDS channels per input/output
Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
Fully buffered unidirectional inputs/outputs
Equalized inputs for operation with long HDMI cables
(20 meters at 2.25 Gbps)
Pre-emphasized outputs
Matched 50 Ω input and output on-chip terminations
Low added jitter
Transmitter disable feature
Reduces power dissipation
Disables input terminations
Single-supply operation (3.3 V)
Standards compliant: HDMI receiver, DVI
40-lead, 6 mm × 6 mm, RoHS-compliant LFCSP
APPLICATIONS
Multiple input displays
Advanced television set (HDTV) front panel connectors
HDMI/DVI cable extenders
FUNCTIONAL BLOCK DIAGRAM
IP[3:0]
IN[3:0]
VTTI
OP[3:0]
AVEE
VTTO
AVCC
ON[3:0]
+
–
+
–
EQ
BUFFER
PE
CONTROL
LOGIC
4
HIGH SPEED
BUFFERED
PE_EN TX_EN
PARALLEL
CONTROL
ADV3003
0
72
12
-0
01
Figure 1.
TYPICAL APPLICATION DIAGRAM
MEDIA CENTER
SET-TOP BOX
DVD PLAYER
HDTV SET
4:1 HDMI
SWITCH
ADV3003
HDMI
RECEIVER
FRONT PANEL
CONNECTOR
BACK PANEL
CONNECTORS
GAME
CONSOLE
0
721
2-
0
02
Figure 2.
GENERAL DESCRIPTION
The ADV3003 is a 4-channel transition minimized differential
signaling (TMDS) buffer featuring equalized inputs and
pre-emphasized outputs. The ADV3003 features 50 Ω input
and output terminations, providing full-swing output signal
recovery and minimizing reflections for improved system
signal integrity. The ADV3003 is targeted at HDMI/DVI
applications and is ideal for use in systems with long cable
runs, long PCB traces, and designs with interior cabling.
The ADV3003 is provided in a 40-lead, LFCSP, surface-mount,
RoHS-compliant, plastic package and is specified to operate
over the 40°C to +85°C temperature range.
PRODUCT HIGHLIGHTS
1.
Supports data rates up to 2.25 Gbps, enabling 1080p deep
color (12-bit color) HDMI formats and greater than UXGA
(1600 × 1200) DVI resolutions.
2.
The 12 dB input cable equalizer enables the use of long
cables at the input. For a typical 24 AWG cable, the
ADV3003 compensates for more than 20 meters at data
rates up to 2.25 Gbps.
3.
The selectable 6 dB of output pre-emphasis allows the
ADV3003 to drive high loss output cables or long PCB traces.
4.
Matched 50 Ω on-chip input and output terminations
improve system signal integrity.
5.
An external control pin, PE_EN, sets the output
pre-emphasis to either 0 dB or 6 dB.
6.
An external control pin, TX_EN, simultaneously disables
both the transmitter and the on-chip input terminations.
This feature reduces the power dissipation of the ADV3003
and indicates to a connected source when the ADV3003 is
disabled.
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