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參數資料
型號: ADV476KN35
廠商: ANALOG DEVICES INC
元件分類: 顯示控制器
英文描述: Circular Connector; No. of Contacts:11; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:19; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:19-11
中文描述: PALETTE-DAC DSPL CTLR, PDIP28
封裝: 0.600 INCH, PLASTIC, DIP-28
文件頁數: 5/12頁
文件大?。?/td> 175K
代理商: ADV476KN35
ADV476
REV. B
–5–
PIN FUNCT ION DE SCRIPT ION
Pin
Mnemonic
Function
BLANK
Composite blank control input (T T L compatible). A logic zero on this control input drives the analog outputs to
the blanking level, as shown in T able V. T he
BLANK
signal is latched on the rising edge of PCLK . While
BLANK
is a logical zero, the pixel inputs are ignored.
Clock input (T T L compatible). T he rising edge of PCLK latches the P0–P7 data inputs and the
BLANK
control
input. It is typically the pixel clock rate of the video system. PCLK should be driven by a dedicated T T L buffer.
Pixel select inputs (T T L compatible). T hese inputs specify, on a pixel basis, which one of the 256 entries in the
color palette RAM is to be used to provide color information. P0–P7 pixel select inputs are latched on the rising
edge of PCLK . P0 is the LSB. Unused pixel select inputs should be connected to GND.
Red, green and blue current outputs. T hese high impedance current sources are capable of directly driving a
doubly terminated 75
coaxial cable, as shown in Figure 4a. All three current outputs should have similar out-
put loads whether or not they are all being used.
Analog power supply (5 V
±
10%).
Analog ground.
Current reference input. T he relationship between the current input and the full scale output voltage of the
DACs is given by the following expression:
I
REF
= VO (Full Scale)/2.15
3
R
L
R
L
= Load Resistance
Write control input (T T L compatible).
WR
must be at logical zero when writing data to the device. D0–D7 data
is latched on the rising edge of
WR
. See Figure 1.
Read control input (T T L compatible).
RD
must both be at logical zero when reading data from the device.
See Figure 1.
Command control inputs (T T L compatible). RS0 and RS1 specify the type of read or write operation being car-
ried out, i.e., address register or color palette RAM read or write operations. See T ables I, II, III.
Data bus (T T L compatible). Data is transferred to and from the address register and the color palette RAM over
this 8-bit bidirectional data bus. D0 is the least significant bit.
PCLK
P0–P7
RED, GREEN,
BLUE
V
CC
GND
I
REF
WR
RD
RS0, RS1
D0–D7
T E RMINOLOGY
Blanking Level
T he level separating the SYNC portion from the Video portion
of the waveform. Usually referred to as the Front Porch or Back
Porch. At 0 IRE Units, it is the level which will shut off the pic-
ture tube, resulting in the blackest possible picture.
Color Video (RGB)
T his usually refers to the technique of combining the three pri-
mary colors of Red, Green and Blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
Gray Scale
T he discrete levels of video signal between Reference Black and
Reference White levels. An 8-bit DAC contains 256 different
levels while a 6-bit DAC contains 64.
Raster Scan
T he most basic method of sweeping a CRT one line at a time to
generate and display images.
Reference Black Level
T he maximum negative polarity amplitude of the video signal.
Reference White Level
T he maximum positive polarity amplitude of the video signal.
Video Signal
T hat portion of the composite video signal which varies in gray
scale levels between Reference White and Reference Black. Also
referred to as the picture signal, this is the portion which may be
visually observed.
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相關代理商/技術參數
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