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參數資料
| 型號： | ADV7120 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS 80 MHz, Triple 8-Bit Video DAC |
| 中文描述： | 80兆赫的CMOS，三8位視頻DAC |
| 文件頁數： | 7/12頁 |
| 文件大小： | 188K |
| 代理商： | ADV7120 |
ADV7120
REV. B
–7–
If we, therefore, have a graphics system with a 1024
×
1024
resolution, a noninterlaced 60 Hz refresh rate and a retrace fac-
tor of 0.8, then:
Dot Rate
= 1024
×
1024
×
60/0.8
= 78.6 MHz
T he required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7120
on the rising edge of CLOCK , as previously described in the
“Digital Inputs” section. It is recommended that the CLOCK
input to the ADV7120 be driven by a T T L buffer (e.g.,
74F244).
92.5 IRE
7.5 IRE
40 IRE
WHITE LEVEL
BLACK LEVEL
BLANK LEVEL
SYNC LEVEL
19.05 0.714 26.67 1.000
1.44 0.054 9.05 0.340
0 0 7.62 0.286
0
0
mA V mA V
RED, BLUE GREEN
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75
LOAD.
2. V
= 1.235V, R
= 560
, I
CONNECTED TO IOG.
3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 3. RGB Video Output Waveform
Video Synchronization and Control
T he ADV7120 has a single composite video sync (
SYNC
) input
control. Many graphics processors and CRT controllers have
the ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC) and composite
SYNC
.
In a graphics system which does not automatically generate a
composite
SYNC
signal, the inclusion of some additional logic
circuitry will enable the generation of a composite
SYNC
signal.
T he I
SYNC
current output is typically connected directly to the
IOG output, thus encoding video synchronization information
onto the green video channel. If it is not required to encode sync
information onto the ADV7120’s analog outputs, the
SYNC
in-
put should be tied to logic low and the I
SYNC
should be con-
nected to analog ground.
Reference Input
An external 1.23 V voltage reference is required to drive
the ADV7120. T he AD589 from Analog Devices is an
ideal choice of reference. It is a two-terminal, low cost,
temperature compensated bandgap voltage reference which
provides a fixed 1.23 V output voltage for input currents
between 50
μ
A and 5 mA. Figure 4 shows a typical refer-
ence circuit connection diagram. T he voltage reference gets
its current drive from the ADV7120’s V
AA
through an on-
board 1 k
resistor to the V
REF
pin. A 0.1
μ
F ceramic ca-
pacitor is required between the COMP pin and V
AA
.
T his is necessary so as to provide compensation for the
internal reference amplifier.
T able I. Video Output T ruth T able
IOG
(mA)
l
IOR, IOB
(mA)
RE F
WHIT E
DAC
Input Data
Description
SYNC
BLANK
WHIT E LEVEL
WHIT E LEVEL
VIDEO
VIDEO to BLANK
BLACK LEVEL
BLACK to BLANK
BLANK LEVEL
SYNC LEVEL
26.67
26.67
video + 9.05
video + 1.44
9.05
1.44
7.62
0
19.05
19.05
video + 1.44
video + 1.44
1.44
1.44
0
0
1
0
0
0
0
0
0
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
0
0
xxH
FFH
data
data
00H
00H
xxH
xxH
NOT E
T ypical with full-scale IOG = 26.67 mA.
V
REF
= 1.235 V, R
SET
= 560
, I
SYNC
connected to IOG.
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