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參數(shù)資料
| 型號： | ADV7120KP80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | CMOS 80 MHz, Triple 8-Bit Video DAC |
| 中文描述： | TRIPLE, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 188K |
| 代理商： | ADV7120KP80 |
ADV7120
REV. B
–5–
PIN FUNCT ION DE SCRIPT ION
Pin
Mnemonic
Function
BLANK
Composite blank control input (T T L compatible). A logic zero on this control input drives the analog out-
puts, IOR, IOB and IOG, to the blanking level. T he
BLANK
signal is latched on the rising edge of CLOCK .
While
BLANK
is a logical zero, the R0–R7, G0–G7, R0–R7 and REF WHIT E pixel and control inputs are
ignored.
SYNC
Composite sync control input (T T L compatible). A logical zero on the
SYNC
input switches off a 40 IRE
current source on the I
SYNC
output.
SYNC
does not override any other control or data input; therefore, it
should only be asserted during the blanking interval.
SYNC
is latched on the rising edge of CLOCK .
CLOCK
Clock input (T T L compatible). T he rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7,
SYNC
,
BLANK
and REF WHIT E pixel and control inputs. It is typically the pixel clock rate of the video system.
CLOCK should be driven by a dedicated T T L buffer.
REF WHIT E
Reference white control input (T T L compatible). A logical one on this input forces the IOR, IOG and IOB
outputs to the white level, regardless of the pixel input data (R0–R7, G0–G7 and B0–B7). REF WHIT E is
latched on the rising edge of clock.
R0–R7,
G0–G7,
B0–B7
Red, green and blue pixel data inputs (T T L compatible). Pixel data is latched on the rising edge of CLOCK .
R0, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
regular PCB power or ground plane.
IOR, IOG, IOB
Red, green, and blue current outputs. T hese high impedance current sources are capable of directly driving
a doubly terminated 75
coaxial cable. All three current outputs should have similar output loads whether
or not they are all being used.
I
SYNC
Sync current output. T his high impedance current source can be directly connected to the IOG output. T his
allows sync information to be encoded onto the green channel. I
SYNC
does not output any current while
SYNC
is at logical zero. T he amount of current output at I
SYNC
while
SYNC
is at logical one is given by:
I
SYNC
(mA) =
3,455
×
V
REF
(V)/ R
SET
(
)
If sync information is not required on the green channel, I
SYNC
should be connected to AGND.
FS ADJUST
Full-scale adjust control. A resistor (R
SET
) connected between this pin and GND, controls the magnitude of
the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output
current.
T he relationship between R
SET
and the full-scale output current on IOG (assuming I
SYNC
is connected to
IOG) is given by:
R
SET
(
) =
12,082
×
V
REF
(V)/IOG (mA)
T he relationship between R
SET
and the full-scale output current on IOR and IOB is given by:
IOR, IOB (mA) =
8,628
×
V
REF
(V)/ R
SET
(
)
Compensation pin. T his is a compensation pin for the internal reference amplifier. A 0.1
μ
F ceramic capaci-
tor must be connected between COMP and V
AA
.
COMP
V
REF
Voltage reference input. An external 1.2 V voltage reference must be connected to this pin. T he use of an ex-
ternal resistor divider network is not recommended. A 0.1
μ
F decoupling ceramic capacitor should be con-
nected between V
REF
and V
AA
.
Analog power supply (5 V
±
5%). All V
AA
pins on the ADV7120 must be connected.
V
AA
GND
Ground. All GND pins must be connected.
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