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參數(shù)資料
型號(hào): ADV7121
廠商: Analog Devices, Inc.
英文描述: CMOS 80 MHz, Triple 10-Bit Video DACs
中文描述: 80兆赫的CMOS,三路10位視頻DAC
文件頁(yè)數(shù): 8/12頁(yè)
文件大小: 196K
代理商: ADV7121
ADV7121/ADV7122
–8–
REV. B
If we, therefore, have a graphics system with a 1024
×
1024
resolution, a noninterlaced 60 Hz refresh rate and a retrace fac-
tor of 0.8, then:
Dot Rate =
1024
×
1024
×
60/0.8
=
78.6 MHz
T he required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7121/
ADV7122 on the rising edge of CLOCK , as previously de-
scribed in the “Digital Inputs” section. It is recommended that
the CLOCK input to the ADV7121/ADV7122 be driven by a
T T L buffer (e.g., 74F244).
92.5 IRE
7.5 IRE
40 IRE
WHITE LEVEL
BLACK LEVEL
BLANK LEVEL
SYNC LEVEL
19.05 0.714 26.67 1.000
1.44 0.054 9.05 0.340
0 0 7.62 0.286
0
0
mA V mA V
RED, BLUE GREEN
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75
LOAD.
2. V
REF
= 1.235V, R
SET
= 560
.
3. RS–343A LEVELS AND TOLERANCES ASSUMED ON ALL
LEVELS.
Figure 3. RGB Video Output Waveform
T able Ia. Video Output T ruth T able for the ADV7122
IOG
(mA)*
IOR, IOB
(mA)
DAC
Input Data
Description
SYNC
BLANK
WHIT E LEVEL
VIDEO
VIDEO to BLANK
BLACK LEVEL
BLACK to BLANK
BLANK LEVEL
SYNC LEVEL
26.67
video + 9.05
video + 1.44
9.05
1.44
7.62
0
19.05
video + 1.44
video + 1.44
1.44
1.44
0
0
1
1
0
1
0
1
0
1
1
1
1
1
0
0
3FFH
data
data
00H
00H
xxH
xxH
*T ypical with full-scale IOG = 26.67 mA. V
REF
= 1.235 V, R
SET
= 560
, I
SYNC
connected to IOG.
T able Ib. Video Output T ruth T able for the ADV7121
IOR, IOG, IOB
(mA)*
DAC
Input Data
Description
WHIT E LEVEL
VIDEO
VIDEO to BLACK
BLACK LEVEL
17.62
video
video
0
3FF
data
data
00H
*T ypical with full scale = 17.62 mA. V
REF
= 1.235 V, R
SET
= 560
.
相關(guān)PDF資料
PDF描述
ADV7122KP30 CMOS 80 MHz, Triple 10-Bit Video DACs
ADV7122KP50 CMOS 80 MHz, Triple 10-Bit Video DACs
ADV7122KP80 CMOS 80 MHz, Triple 10-Bit Video DACs
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ADV7122 80 MHz, Triple 10-Bit Video DACs(80MHz,三通道10位視頻D/A轉(zhuǎn)換器)
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