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參數資料
| 型號： | ADV7176A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder |
| 中文描述： | 高品質，10位，數字無線電咨詢委員會，601到PAL / NTSC制式視頻編碼器 |
| 文件頁數： | 22/52頁 |
| 文件大小： | 629K |
| 代理商： | ADV7176A |
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ADV7175A/ADV7176A
–22–
REV. B
T he ADV7175A/ADV7176A acts as a standard slave device on
the bus. T he data on the SDAT A pin is 8 bits long, supporting
the 7-bit addresses, plus the R/
W
bit. T he ADV7175A has 33
subaddresses and the ADV7176A has 19 subaddresses to enable
access to the internal registers. It therefore interprets the first
byte as the device address and the second byte as the starting
subaddress. T he subaddresses auto increment allow data to
be written to or read from the starting subaddress. A data
transfer is always terminated by a stop condition. T he user can
also access any unique subaddress register on a one by one basis
without having to update all the registers. T here is one excep-
tion. T he subcarrier frequency registers should be updated in
sequence, starting with Subcarrier Frequency Register 0. T he
auto increment function should then be used to increment and
access Subcarrier Frequency Registers 1, 2 and 3. T he subcarrier
frequency registers should not be accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high pe-
riod, the user should issue only one start condition, one stop
condition or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7175A/ADV7176A will not issue an acknowledge and will
DATA
A(S)
S
SLAVE ADDR A(S)
SUB ADDR
A(S)
LSB = 0
LSB = 1
DATA
A(S) P
S
SLAVE ADDR A(S)
SUB ADDR
A(S) S
SLAVE ADDR
A(S)
DATA
A(M)
A
(M)
DATA
P
WRITE
SEQUENCE
READ
SEQUENCE
A
(S) = NO-ACKNOWLEDGE BY SLAVE
A
(M) = NO-ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
Figure 30. Write and Read Sequences
SR4
SR3
SR2
SR1
SR0
SR7
SR6
SR5
SR5
SR4 SR3 SR2 SR1 SR0
ADV7175A SUBADDRESS REGISTER
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
" "
" "
1
MACROVISION REGISTER
0
TTXRQ CONTROL REGISTER 0
MODE REGISTER 0
MODE REGISTER 1
SUB CARRIER FREQ REGISTER 0
SUB CARRIER FREQ REGISTER 1
SUB CARRIER FREQ REGISTER 2
SUB CARRIER FREQ REGISTER 3
SUB CARRIER PHASE REGISTER
TIMING REGISTER 0
CLOSED CAPTIONING EXTENDED DATA
<
BYTE 0
CLOSED CAPTIONING EXTENDED DATA
<
BYTE 1
CLOSED CAPTIONING DATA
<
BYTE 0
CLOSED CAPTIONING DATA
<
BYTE 1
TIMING REGISTER 1
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)/TTX SETUP REG 0*
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)/TTX SETUP REG 1*
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)/TTX SETUP REG 2*
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)/TTX SETUP REG 3*
MODE REGISTER 3
MACROVISION REGISTER
*TTX REGISTERS ARE AVAILABLE IN PAL MODE ONLY
IN NTSC MODE THESE REGISTERS CONTROL PEDESTAL
ZERO SHOULD BE WRITTEN
TO THESE BITS
SR7–SR6 (00)
SR5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SR4 SR3 SR2 SR1 SR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
1
0
0
1
0
0
0
0
1
ADV7176A SUBADDRESS REGISTER
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
MODE REGISTER 0
MODE REGISTER 1
SUB CARRIER FREQ REGISTER 0
SUB CARRIER FREQ REGISTER 1
SUB CARRIER FREQ REGISTER 2
SUB CARRIER FREQ REGISTER 3
SUB CARRIER PHASE REGISTER
TIMING REGISTER 0
CLOSED CAPTIONING EXTENDED DATA
<
BYTE 0
CLOSED CAPTIONING EXTENDED DATA
<
BYTE 1
CLOSED CAPTIONING DATA
<
BYTE 0
CLOSED CAPTIONING DATA
<
BYTE 1
TIMING REGISTER 1
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)/TTX SETUP REG 0*
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)/TTX SETUP REG 1*
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)/TTX SETUP REG 2*
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)/TTX SETUP REG 3*
MODE REGISTER 3
TTXRQ CONTROL REGISTER 0
*TTX REGISTERS ARE AVAILABLE IN PAL MODE ONLY
IN NTSC MODE THESE REGISTERS CONTROL PEDESTAL
Figure 31. Subaddress Register
return to the idle condition. If, in auto-increment mode the user
exceeds the highest subaddress, the following action will be
taken:
1. In Read Mode, the highest subaddress register contents will
continue to be output until the master device issues a no-
acknowledge. T his indicates the end of a read. A no-ac-
knowledge condition is where the SDAT A line is not pulled
low on the ninth pulse.
2. In Write Mode, the data for the invalid byte will not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7175A/ADV7176A and the part will
return to the idle condition.
1-7
8
9
1-7
8
9
1-7
8
9
P
S
START ADDR R/
W
ACK SUBADDRESS ACK
DATA
ACK
STOP
SDATA
SCLOCK
Figure 29. Bus Data Transfer
Figure 29 illustrates an example of data transfer for a read se-
quence and the start and stop conditions.
Figure 30 shows bus write and read sequences.
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