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參數資料
| 型號： | ADV7179 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
| 中文描述： | 芯片級PAL / NTSC制式視頻編碼器與高級電源管理 |
| 文件頁數： | 34/52頁 |
| 文件大小： | 488K |
| 代理商： | ADV7179 |
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ADV7174/ADV7179
TIMING MODE REGISTER 1 (TR1)
Bits:
TR17–TR10
Address:
SR4–SR0 = 08H
Rev. A | Page 34 of 52
Timing Register 1 is an 8-bit-wide register. Figure 44 shows the various operations under the control of Timing Register 1. This register
can be read from as well written to. This register can be used to adjust the width and position of the master mode timing signals.
TR11
TR10
TR17
TR12
TR13
TR15
TR16
TR14
HSYNC TO PIXEL
DATA ADJUST
TR17 TR16
0
0
1
1
0
×
T
PCLK
1
×
T
PCLK
2
×
T
PCLK
3
×
T
PCLK
1
×
T
PCLK
4
×
T
PCLK
16
×
T
PCLK
128
×
T
PCLK
0
×
T
PCLK
4
×
T
PCLK
8
×
T
PCLK
16
×
T
PCLK
1
×
T
PCLK
4
×
T
PCLK
16
×
T
PCLK
128
×
T
PCLK
0
1
0
1
HSYNC TO
FIELD/VSYNC DELAY
TR13 TR12
0
0
1
1
0
1
0
1
HSYNC WIDTH
0
0
1
1
0
1
0
1
TR11 TR10
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
x
x
T
B
T
B
+ 32
μ
s
0
1
TR15 TR14
T
C
T
A
T
B
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0
1
1
0
1
0
1
LINE 313
LINE 314
LINE 1
TIMING MODE 1 (MASTER/PAL)
HSYNC
FIELD/VSYNC
T
B
T
A
T
C
0
Figure 44. Timing Register 1
Table 16. TR1 Bit Description
Bit Name
HSYNC Width
HSYNC to FIELD/VSYNC
Delay
HSYNC to FIELD Rising
Edge Delay
VSYNC Width
Bit No.
TR11–TR10
TR13–TR12
Description
These bits adjust the HSYNC pulse width.
These bits adjust the position of the HSYNC output relative to the FIELD/VSYNC output.
TR15–TR14
When the ADV7174/ADV7179 is in Timing Mode 1, these bits adjust the position of the HSYNC
output relative to the FIELD output rising edge.
When the ADV7174/ADV7179 is configured in Timing Mode 2, these bits adjust the VSYNC
pulse width.
This enables the HSYNC to be adjusted with respect to the pixel data. This allows the Cr and Cb
components to be swapped. This adjustment is available in both master and slave timing modes.
TR15–TR14
HSYNC to Pixel Data Adjust
TR17–TR16
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