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參數資料
| 型號： | ADV7179BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
| 中文描述： | COLOR SIGNAL ENCODER, QCC40 |
| 封裝： | 6 X 6 MM, MO-220VJJD-2, LFCSP-40 |
| 文件頁數： | 40/52頁 |
| 文件大小： | 488K |
| 代理商： | ADV7179BCP |
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ADV7174/ADV7179
SUPPLY DECOUPLING
For optimum performance, bypass capacitors should be in-
stalled using the shortest leads possible, consistent with reliable
operation, to reduce the lead inductance. Best performance is
obtained with 0.1 μF ceramic capacitor decoupling. Each group
of V
AA
pins on the ADV7174/ADV7179 must have at least one
0.1 μF decoupling capacitor to GND. These capacitors should be
placed as close to the device as possible.
Rev. A | Page 40 of 52
It is important to note that while the ADV7174/ADV7179
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to
reducing power supply noise and consider using a 3-terminal
voltage regulator for supplying power to the analog power
plane.
DIGITAL SIGNAL INTERCONNECT
The digital inputs to the ADV7174/ADV7179 should be isolated
as much as possible from the analog outputs and other analog
circuitry. Also, these input signals should not overlay the analog
power plane.
Due to the high clock rates involved, long clock lines to the
ADV7174/ADV7179 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (V
CC
) and not to the
analog power plane.
ANALOG SIGNAL INTERCONNECT
The ADV7174/ADV7179 should be located as close to the
output connectors as possible to minimize noise pickup and
reflections due to impedance mismatch.
The video output signals should overlay the ground plane, not
the analog power plane, to maximize the high frequency power
supply rejection.
Digital inputs, especially pixel data inputs and clocking signals,
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
For best performance, the outputs should each have a 75 load
resistor connected to GND. These resistors should be placed as
close as possible to the ADV7174/ADV7179 to minimize
reflections.
The ADV7174/ADV7179 should have no inputs left floating.
Any inputs that are not required should be tied to ground.
The circuit in Figure 55 can be used to generate a 13.5 MHz
waveform using the 27 MHz clock and the HSYNC pulse. This
waveform is guaranteed to produce the 13.5 MHz clock in
synchronization with the 27 MHz clock. This 13.5 MHz clock
can be used if the 13.5 MHz clock is required by the MPEG
decoder. This guarantees that the Cr and Cb pixel information
is input to the ADV7174/ADV7179 in the correct sequence.
Note that the exposed metal paddle on the bottom side of the
LFCSP package must be soldered to PCB ground for proper
heat dissipation and also for electrical noise and mechanical
strength benefits.
D
Q
CK
D
Q
CK
CLOCK
HSYNC
13.5MHz
0
Figure 55. Circuit to Generate 13.5 MHz
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| ADV7175A | High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7179BCP1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
| ADV7179BCP-REEL | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 10-Bit 40-Pin LFCSP EP T/R |
| ADV7179BCP-REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
| ADV7179BCPZ | 功能描述:IC ENCODER VID NTSC/PAL 40LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7179BCPZ2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
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