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參數資料
| 型號： | ADV7181 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SDTV Video Decoder |
| 中文描述： | 標清多格式視頻解碼器 |
| 文件頁數： | 60/96頁 |
| 文件大小： | 873K |
| 代理商： | ADV7181 |
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ADV7181B
REGISTER ACCESSES
The MPU can write to or read from all of the ADV7181B’s
registers, except the Subaddress register, which is write-only.
The Subaddress register determines which register the next read
or write operation accesses. All communications with the part
through the bus start with an access to the Subaddress register.
Then, a read/write operation is performed from/to the target
address, which then increments to the next address until a stop
command on the bus is performed.
Rev. 0 | Page 60 of 96
REGISTER PROGRAMMING
The following sections describe each register in terms of its
configuration. The Communications register is an 8-bit, write-
only register. After the part has been accessed over the bus and a
read/write operation is selected, the subaddress is set up. The
Subaddress register determines to/from which register the
operation takes place. Table 81 lists the various operations
under the control of the Subaddress register for the control port.
Register Select (SR7–SR0)
These bits are set up to point to the required starting address.
I
2
C SEQUENCER
An I
2
C sequencer is used when a parameter exceeds eight bits,
and is therefore distributed over two or more I
2
C registers, for
example, HSB [11:0].
When such a parameter is changed using two or more I
2
C write
operations, the parameter may hold an invalid value for the
time between the first I
2
C being completed and the last I
2
C
being completed. In other words, the top bits of the parameter
may already hold the new value while the remaining bits of the
parameter still hold the previous value.
To avoid this problem, the I
2
C sequencer holds the already
updated bits of the parameter in local memory; all bits of the
parameter are updated together once the last register write
operation has completed.
The correct operation of the I
2
C sequencer relies on the
following:
All I
2
C registers for the parameter in question must be
written to in order of ascending addresses. For example, for
HSB[10:0], write to Address 0x34 first, followed by 0x35.
No other I
2
C taking place between the two (or more) I
2
C
writes for the sequence. For example, for HSB[10:0], write
to Address 0x34 first, immediately followed by 0x35.
相關PDF資料 |
PDF描述 |
|---|---|
| ADV7181B | Multiformat SDTV Video Decoder |
| ADV7181BBCPZ | Multiformat SDTV Video Decoder |
| ADV7181BBSTZ | Multiformat SDTV Video Decoder |
| ADV7181BCP | Multiformat SDTV Video Decoder |
| ADV7181BST | Multiformat SDTV Video Decoder |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7181B | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7181BBCPZ | 制造商:Analog Devices 功能描述:Video Decoder 3ADC 9-Bit 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:ADV718XB DECODER FAMILY UPDATES - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7181BBSTZ | 制造商:Analog Devices 功能描述:Video Decoder 3ADC 9-Bit 64-Pin LQFP 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7181BCP | 制造商:Analog Devices 功能描述:Video Decoder 3ADC 9-Bit 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10BIT NTSC/PAL/SECAM VIDEO DECODER I.C. - Bulk |
| ADV7181BCPZ | 制造商:Analog Devices 功能描述: |
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