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參數資料
| 型號： | ADV7181BST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Multiformat SDTV Video Decoder |
| 中文描述： | COLOR SIGNAL DECODER, PQFP64 |
| 封裝： | LEAD FREE, MS-026BCD, LQFP-64 |
| 文件頁數： | 42/96頁 |
| 文件大小： | 873K |
| 代理商： | ADV7181BST |
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ADV7181B
NVENDDELE NTSC VSync End Delay on Even Field,
Address 0xE6 [6]
Rev. 0 | Page 42 of 96
When NVENDDELE is set to 0 (default), there is no delay.
Setting NVENDDELE to 1 delays VSync from going low on an
even field by a line relative to NVEND.
NVENDSIGN NTSC VSync End Sign, Address 0xE6 [5]
Setting NVENDSIGN to 0 (default) delays the end of VSync. Set
for user manual programming.
Setting NVENDSIGN to 1 advances the end of VSync. Not
recommended for user programming.
NVEND NTSC[4:0] VSync End, Address 0xE6 [4:0]
The default value of NVEND is 00100, indicating the NTSC
VSync end position.
For all NTSC/PAL VSync timing controls, both the V bit in the
AV code and the VSync on the VS pin are modified.
NFTOGDELO NTSC Field Toggle Delay on Odd Field,
Address 0xE7 [7]
When NFTOGDELO is 0 (default), there is no delay.
Setting NFTOGDELO to 1 delays the field toggle/transition on
an odd field by a line relative to NFTOG.
NFTOGDELE NTSC Field Toggle Delay on Even Field,
Address 0xE7 [6]
When NFTOGDELE is 0, there is no delay.
Setting NFTOGDELE to 1 (default) delays the field toggle/
transition on an even field by a line relative to NFTOG.
0
ADVANCE TOGGLE OF
FIELD BY NFTOG[4:0]
DELAY TOGGLE OF
FIELD BY NFTOG[4:0]
NFTOGSIGN
ODD FIELD
0
1
NO
YES
NFTOGDELE
ADDITIONAL
DELAY BY
1 LINE
1
0
NFTOGDELO
ADDITIONAL
DELAY BY
1 LINE
1
0
FIELD
TOGGLE
NOT VALID FOR USER
PROGRAMMING
Figure 24. NTSC FIELD Toggle
NFTOGSIGN NTSC Field Toggle Sign, Address 0xE7 [5]
Setting NFTOGSIGN to 0 delays the field transition. Set for
user manual programming.
Setting NFTOGSIGN to 1 (default) advances the field
transition. Not recommended for user programming.
NFTOG[4:0] NTSC Field Toggle, Address 0xE7 [4:0]
The default value of NFTOG is 00011, indicating the NTSC
Field toggle position.
For all NTSC/PAL Field timing controls, both the F bit in the
AV code and the Field signal on the FIELD/DE pin are modified.
Table 55. Recommended User Settings for PAL
(see Figure 26)
Register
Register Name
0x31
VSync Field Control 1
0x32
VSync Field Control 2
0x33
VSync Field Control 3
0x37
Polarity
0xE8
PAL_V_Bit_Beg
0xE9
PAL_V_Bit_End
0xEA
PAL_F_Bit_Tog
Write
0x12
0x81
0x84
0x29
0x1
0x4
0x6
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| ADV7183B | Multiformat SDTV Video Decoder |
| ADV7183BBSTZ | Multiformat SDTV Video Decoder |
| ADV7183BKSTZ | Multiformat SDTV Video Decoder |
| ADV7183KST | Advanced Video Decoder with 10-Bit ADC and Component Input Support |
| AD7183 | Advanced Video Decoder with 10-Bit ADC and Component Input Support |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7181C | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, Integrated, Multiformat SDTV Video Decoder and RGB Graphics Digitizer |
| ADV7181CBCPZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADV7181CBCPZ-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, Integrated, Multiformat SDTV Video Decoder and RGB Graphics Digitizer |
| ADV7181CBSTZ | 功能描述:IC VIDEO DECODER SDTV RGB 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7181CBSTZ-REEL | 功能描述:IC VIDEO DECODER SDTV RGB 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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