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參數(shù)資料
| 型號： | ADV7183BKSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Multiformat SDTV Video Decoder |
| 中文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | LEAD FREE, MS-026-BEC, LQFP-80 |
| 文件頁數(shù)： | 47/100頁 |
| 文件大小： | 844K |
| 代理商： | ADV7183BKSTZ |
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ADV7183B
VBI DATA DECODE
The following low data rate VBI signals can be decoded by the
ADV7183B:
Rev. B | Page 47 of 100
Wide screen signaling (WSS)
Copy generation management systems (CGMS)
Closed captioning (CCAP)
EDTV
Gemstar 1×- and 2×-compatible data recovery
The presence of any of the above signals is detected and, if
applicable, a parity check is performed. The result of this testing
is contained in a confidence bit in the VBI Info[7:0] register.
Users are encouraged to first examine the VBI Info register
before reading the corresponding data registers. All VBI data
decode bits are read only.
All VBI data registers are double-buffered with the field signals.
This means that data is extracted from the video lines and
appears in the appropriate I
2
C registers with the next field
transition. They are then static until the next field.
The user should start an I
2
C read sequence with VS by first
examining the VBI Info register. Then, depending on what data
was detected, the appropriate data registers should be read.
Note that the data registers are filled with decoded VBI data
even if their corresponding detection bits are low; it is likely
that bits within the decoded data stream are wrong.
The closed captioning data (CCAP) is available in the I
2
C
registers and is also inserted into the output video data stream
during horizontal blanking.
The Gemstar-compatible data is not available in the I
2
C
registers and is inserted into the data stream only during
horizontal blanking.
WSSD Wide Screen Signaling Detected, Address 0x90[0]
Logic 1 for this bit indicates the data in the WSS1 and WSS2
registers is valid.
The WSSD bit goes high if the rising edge of the start bit is
detected within a time window and if the polarity of the parity
bit matches the data transmitted.
When WSSD is 0, no WSS is detected and confidence in the
decoded data is low.
When WSSD is 1, WSS is detected and confidence in the
decoded data is high.
CCAPD Closed Caption Detected, Address 0x90[1]
A Logic 1 for this bit indicates that the data in the CCAP1 and
CCAP2 registers is valid.
The CCAPD bit goes high if the rising edge of the start bit is
detected within a time window and if the polarity of the parity
bit matches the data transmitted.
When CCAPD is 0, no CCAP sequences are detected and
confidence in the decoded data is low.
When CCAPD is 1, the CCAP sequence is detected and
confidence in the decoded data is high.
EDTVD EDTV Sequence Detected, Address 0x90[2]
A Logic 1 for this bit indicates the data in the EDTV1, 2, 3
registers is valid.
The EDTVD bit goes high if the rising edge of the start bit is
detected within a time window and if the polarity of the parity
bit matches the data transmitted.
When EDTVD is 0, no EDTV sequence is detected and
confidence in the decoded data is low.
When EDTVD is 1, an EDTV sequence is detected and
confidence in the decoded data is high.
CGMSD CGMS-A Sequence Detected, Address 0x90[3]
Logic 1 for this bit indicates that the data in the CGMS1, 2, 3
registers is valid. The CGMSD bit goes high if a valid CRC
checksum has been calculated from a received CGMS packet.
When CGMSD is 0, no CGMS transmission is detected and
confidence in the decoded data is low.
When CGMSD is 1, the CGMS sequence is decoded and
confidence in the decoded data is high.
CRC_ENABLE CRC, Address 0xB2[2]
For certain video sources, the CRC data bits can have an invalid
format. In these circumstances, the CRC checksum validation
procedure can be disabled. The CGMSD bit goes high if the
rising edge of the start bit is detected within a time window.
When CRC_ENABLE is 0, no CRC check is performed. The
CGMSD bit goes high if the rising edge of the start bit is
detected within a time window.
When CRC_ENABLE is 1 (default), CRC checksum is used to
validate the CGMS sequence. The CGMSD bit goes high for a
valid checksum. The default is ADI’s recommended setting.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7183KST | 制造商:Analog Devices 功能描述:Video Decoder 2ADC 10-Bit 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:VIDEO DECODER I.C. - Bulk |
| ADV7184 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder with Fast Switch Overlay Support |
| ADV7184BSTZ | 功能描述:IC DECODER VID SDTV MULTI 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7185 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
| ADV7185KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
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