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參數資料
| 型號： | ADV7194 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
| 中文描述： | 專業擴展- 10⑩視頻編碼器，54兆赫采樣 |
| 文件頁數： | 33/69頁 |
| 文件大小： | 647K |
| 代理商： | ADV7194 |
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ADV7194
–33–
REV. 0
MODE REGISTER 5
MR5 (MR57–MR50)
(Address (SR4–SR0) = 05H)
Mode Register 5 is an 8-bit-wide register. Figure 60 shows
the various operations under the control of Mode Register 5.
MR5 BIT DESCRIPTION
Y-Level Control (MR50)
This bit controls the component Y output level on the ADV7194.
If this bit is set (0), the encoder outputs Betacam levels when
configured in PAL or NTSC mode. If this bit is set (1), the
encoder outputs SMPTE levels when configured in PAL or
NTSC mode.
UV-Level Control (MR51–MR52)
These bits control the component U and V output levels on
the ADV7194. It is possible to have UV levels with a peak-to-
peak amplitude of either 700 mV (MR52 + MR51 = 01 ) or
1000 mV (MR52 + MR51 = 10) in NTSC and PAL. It is also
possible to have default values of 934 mV for NTSC and 700 mV
for PAL (MR52 + MR51 = 00).
RGB Sync (MR53)
This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
Clamp Delay (MR54–MR55)
These bits control the delay or advance of the CLAMP signal in
the front or back porch of the ADV7194. It is possible to delay or
advance the pulse by zero, one, two, or three clock cycles.
Note: TTX functionality is shared with
VSO
and CLAMP on Pin
62. CLAMP/
VSO
Select (MR77) and TTX Input/CLAMP/
VSO
Output (MR76) have to be set accordingly.
Clamp Delay Direction (MR56)
This bit controls a positive or negative delay in the CLAMP sig-
nal. If this bit is set (1), the delay is negative. If it is set (0), the
delay is positive.
Clamp Position (MR57)
This bit controls the position of the CLAMP signal. If this bit is
set (1), the CLAMP signal is located in the back porch position.
If this bit is set (0), the CLAMP signal is located in the front
porch position.
MR57
MR56
MR55
MR54
MR53
MR52
MR51
MR50
0
1
POSITIVE
NEGATIVE
MR56
CLAMP DELAY
DIRECTION
UV-LEVEL CONTROL
MR52 MR51
0 0 DEFAULT LEVELS
0
1
700mV
1
0
1000mV
1
1
RESERVED
0
1
DISABLE
ENABLE
MR53
RGB SYNC
CLAMP
POSITION
0
1
FRONT PORCH
BACK PORCH
MR57
0
1
DISABLE
ENABLE
MR50
Y-LEVEL
CONTROL
CLAMP DELAY
MR55 MR54
0 0 NO DELAY
0
1
1
0
1
1
1 PCLK
2 PCLK
3 PCLK
Figure 60. Mode Register 5, MR5
MR47
MR46
MR45
MR44
MR43
MR42
MR41
MR40
0
1
DISABLE
ENABLE
MR46
COLOR BAR
CONTROL
CHROMINANCE
CONTROL
MR44
0
1
ENABLE COLOR
DISABLE COLOR
GENLOCK CONTROL
MR42 MR41
0 0 DISABLE GENLOCK
0
1
ENABLE SUBCARRIER
RESET PIN
1
0
TIMING RESET
1
1
ENABLE RTC PIN
0
1
DISABLE
ENABLE
MR40
VSYNC 3H
CONTROL
BURST
CONTROL
0
1
ENABLE BURST
DISABLE BURST
MR45
ACTIVE VIDEO
LINE DURATION
0
1
720 PIXELS
710 PIXELS/702 PIXELS
MR43
INTERLACED
MODE CONTROL
MR47
0
1
INTERLACED
NONINTERLACED
Figure 59. Mode Register 4, MR4
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7194KST | 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:PROFESSIONAL/HDTV NTSC/PAL ENCODER I.C. - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7194KSTZ | 功能描述:IC ENCODER VIDEO EXT-10 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7194KSTZ | 制造商:Analog Devices 功能描述:TV / Video IC |
| ADV7195 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| ADV7195KS | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT VID+PROGSCAN/HDTV ENCODERIC - Bulk |
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