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參數資料
| 型號： | ADV7300AKST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | PLASTIC, MS-026BCD, LQFP-64 |
| 文件頁數： | 35/68頁 |
| 文件大小： | 1544K |
| 代理商： | ADV7300AKST |
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REV. A
ADV7300A/ADV7301A
–35–
VERTICAL BLANKING INTERVAL
The ADV7300A/ADV7301A accepts input data that contains
VBI data [CGMS, WSS, VITS, etc.] in SD and HD Modes.
For SMPTE293M (525 p) standards, VBI data can be inserted on
Lines 13 to 42 of each frame, or Lines 6 to 43 for ITU-R.BT1358
(625 p) standard.
For SD NTSC, this data can be present on Lines 10 to 20, in
PAL on Lines 7 to 22.
If VBI is disabled [Address 11h, Bit 4 for HD; Address 43h,
Bit 4 for SD], VBI data is not present at the output and the
entire VBI is blanked. These control bits are valid in all master
and slave modes.
In Slave Mode 0, if VBI is enabled, the Blanking Bit in the
EAV/SAV code is overwritten and it is possible to use VBI in
this timing mode as well.
In Slave Mode 1 or 2, the
BLANK
Control Bit must be set to
enabled [Address 4Ah, Bit 3] to allow VBI data to pass through
the ADV7300A/ADV7301A. Otherwise, the ADV7300A/
ADV7301A automatically blanks the VBI to standard.
If CGMS is enabled and VBI disabled, the CGMS data will
nevertheless be available at the output.
SD SUBCARRIER FREQUENCY REGISTERS
[Subaddress 4Ch–4Fh]
Four 8-bit wide registers are used to set up the subcarrier fre-
quency. The value of these registers is calculated in using the
equation:
Subcarrier Frequency Register =
#
#
of
MHz Clock Cycles in One Video Line
27
of Subcarrier Frequency Cycles in One Video Line
2
32
×
Example:
NTSC Mode
Subcarrier Frequency =
227 5
1716
2
569408542
32
.
*
×
=
Subcarrier Register Value = 21F07C1Eh
SD F
SC
Register 0: 1Eh
SD F
SC
Register 1: 7Ch
SD F
SC
Register 2: F0h
SD F
SC
Register 3: 21h
Refer to the MPU Port Description section for more detail on
how to access the subcarrier frequency registers.
SUBCARRIER PHASE REGISTER
[Subaddress 50h, 5Ch, Bits 7, 6]
Ten bits are used to set up the subcarrier phase. Each bit repre-
sents 0.352
°
. For normal operation, this register is set to 00h.
FILTERS
Table XV shows an overview of the programmable filters avail-
able on the ADV7300A/ADV7301A.
Table XV. Selectable Filters
Filter
Subaddress
SD Luma LPF NTSC
SD Luma LPF PAL
SD Luma Notch NTSC
SD Luma Notch PAL
SD Luma SSAF
SD Luma CIF
SD Luma QCIF
SD Chroma 0.65 MHz
SD Chroma 1.0 MHz
SD Chroma 1.3 MHz
SD Chroma 2.0 MHz
SD Chroma 3.0 MHz
SD Chroma CIF
SD Chroma QCIF
SD UV SSAF
HD Chroma Input
HD Sync Filter
HD Chroma SSAF
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
42h
13h
13h
13h
HD Sync Filter
FREQUENCY – MHz
0.5
–0.50
30
5
G
10
15
20
25
0.4
0.1
–0.2
–0.3
–0.4
0.3
0.2
0
–0.1
Figure 31. HD Sync Filter Enabled
FREQUENCY – MHz
0.5
–0.50
30
5
G
10
15
20
25
0.4
0.1
–0.2
–0.3
–0.4
0.3
0.2
0
–0.1
Figure 32. HD Sync Filter Disabled
*
Rounded to the nearest integer
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相關代理商/技術參數 |
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|---|---|
| ADV7301A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| ADV7301AKST | 功能描述:IC DAC VIDEO HDTV 6-12BIT 64LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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