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參數資料
| 型號： | ADV7321 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
| 中文描述： | 多格式視頻編碼器216兆赫六噪聲整形的12位DAC |
| 文件頁數： | 34/88頁 |
| 文件大小： | 1002K |
| 代理商： | ADV7321 |
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ADV7320/ADV7321
Table 17. Registers 0x4A to 0x58
SR7–
SR0
Register
0x4A
SD Timing
Register 0
Rev. 0 | Page 34 of 88
Bit Description
SD Slave/Master
Mode
SD Timing Mode
Bit 7
x
Bit 6
0
1
0
Bit 5
0
0
1
1
0
Bit 4
0
1
0
1
0
Bit 3
0
1
0
Bit 2
0
0
1
1
0
Bit 1
0
1
0
1
0
Bit 0
0
1
0
Register Setting
Slave mode.
Master mode.
Mode 0.
Mode 1.
Mode 2.
Mode 3.
Enabled.
Disabled.
No delay.
2 clk cycles.
4 clk cycles.
6 clk cycles.
40 IRE.
7.5 IRE.
A low-high-low transition will
reset the internal SD timing
counters.
T
a
= 1 clk cycle.
T
a
= 4 clk cycles.
T
a
= 16 clk cycles.
T
a
= 128 clk cycles.
T
b
= 0 clk cycle.
T
b
= 4 clk cycles.
T
b
= 8 clk cycles.
T
b
= 18 clk cycles.
T
c
= T
b
.
T
c
= T
b
+ 32 μs.
Reset
Value
0x08
SD BLANK Input
SD Luma Delay
SD Min. Luma
Value
SD Timing Reset
x
x
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
SD HSYNC Width
0x00
SD HSYNCto
VSYNC Delay
SD HSYNC to VSYNC
Rising Edge Delay
(Mode 1 Only)
VSYNC Width
(Mode 2 Only)
0
0
1
1
x
x
x
x
x
x
0
1
0
1
x
x
x
x
x
x
0
0
1
1
x
x
x
x
x
x
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1 clk cycle.
4 clk cycles.
16 clk cycles.
128 clk cycles.
0 clk cycles.
1 clk cycle.
2 clk cycles.
3 clk cycles.
Subcarrier Frequency Bits 7 to 0.
Subcarrier Frequency Bits 15 to 8.
Subcarrier Frequency Bits 23 to 16.
Subcarrier Frequency Bits 31 to 24.
Subcarrier Phase Bits 9 to 2.
Extended Data Bits 7 to 0.
0x4B
SD Timing
Register 1
HSYNC to Pixel
Data Adjust
0x4C
0x4D
0x4E
0x4F
0x50
0x51
SD F
SC
Register 0
1
SD F
SC
Register 1
SD F
SC
Register 2
SD F
SC
Register 3
SD F
SC
Phase
SD Closed
Captioning
SD Closed
Captioning
SD Closed
Captioning
SD Closed
Captioning
SD Pedestal
Register 0
Extended Data on
Even Fields
Extended Data on
Even Fields
Data on Odd Fields
0x1E
1
0x7C
0xF0
0x21
0x00
0x00
0x52
x
x
x
x
x
x
x
x
Extended Data Bits 15 to 8.
0x00
0x53
x
x
x
x
x
x
x
x
Data Bits 7 to 0.
0x00
0x54
Data on Odd Fields
x
x
x
x
x
x
x
x
Data Bits 15 to 8.
0x00
0x55
Pedestal on Odd
Fields
17
16
15
14
13
12
11
10
Setting any of these bits to 1 will
disable pedestal on the line num-
ber indicated by the bit settings.
0x00
0x56
SD Pedestal
Register 1
SD Pedestal
Register 2
SD Pedestal
Register 3
Pedestal on Odd
Fields
Pedestal on Even
Fields
Pedestal on Even
Fields
25
24
23
22
21
20
19
18
0x00
0x57
17
16
15
14
13
12
11
10
0x00
0x58
25
24
23
22
21
20
19
18
0x00
1
For precise NTSC Fsc, this register should be programmed to 0x1F.
LINE 313
LINE 314
LINE 1
t
B
t
A
t
C
0
HSYNC
VSYNC
Figure 48. Timing Register 1 in PAL Mode
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