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參數資料
型號: ADV7392
廠商: Analog Devices, Inc.
英文描述: Low Power, Chip Scale 10-Bit SD/HD Video Encoder
中文描述: 低功耗,芯片尺寸10位標清/高清視頻編碼器
文件頁數: 42/96頁
文件大小: 1209K
代理商: ADV7392
ADV7390/ADV7391/ADV7392/ADV7393
ADV7392/ADV7393 INPUT CONFIGURATION
The ADV7392/ADV7393 supports a number of different input
modes. The desired input mode is selected using Subaddress 0x01,
Bits[6:4]. The ADV7392/ADV7393 defaults to standard
definition (SD) mode upon power-up. Table 31 provides an
overview of all possible input configurations. Each input mode
is described in detail in this section.
STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
SD YCrCb data can be input in 4:2:2 format over an 8-, 10-, or 16-
bit bus. SD RGB data can be input in 4:4:4 format over a 16-bit bus.
A 27 MHz clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported in 8-bit and 10-bit modes.
8-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0
Subaddress 0x88, Bits[4:3] = 00
In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin P15 to Pin P8, with P8 being the LSB. The ITU-R
BT.601/656 input standard is supported.
10-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0
Subaddress 0x88, Bits[4:3] = 10
In 10-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin P15 to Pin P6, with P6 being the LSB. The ITU-R
BT.601/656 input standard is supported.
Rev. 0 | Page 42 of 96
16-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0
Subaddress 0x88, Bits[4:3] = 01
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin P15 to Pin P8, with P8 being the LSB.
The CrCb pixel data is input on Pin P7 to Pin P0, with P0 being
the LSB.
The pixel data is updated at half the rate of the clock, that is, at a
rate of 13.5 MHz (see Figure 3).
16-Bit 4:4:4 RGB Mode
Subaddress 0x87, Bit 7 = 1
In 16-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin P4 to Pin P0, the green pixel data is input on Pin P10 to
Pin P5, and the blue pixel data is input on Pin P15 to Pin P11.
P0, P5, and P11 are the respective bus LSBs.
The pixel data is updated at half the rate of the clock, that is, at a
rate of 13.5 MHz (see Figure 4).
MPEG2
DECODER
CLKIN
P[15:8]/P[15:6]
27MHz
YCrCb
ADV7392/
ADV7393
VSYNC,
HSYNC
2
8/10
0
Figure 54. SD Example Application
Table 31. ADV7392/ADV7393 Input Configuration
Input Mode
1
000
SD
2
8-Bit
10-Bit
16-Bit
3
16-Bit
3
001
ED/HD-SDR (16-Bit)
010
ED/HD-DDR
4
8-Bit
10-Bit
111
ED (At 54 MHz)
8-Bit
10-Bit
1
The input mode is determined by Subaddress 0x01, Bits[6:4].
2
In SD mode, the width of the input data is determined by Subaddress 0x88, Bits[4:3].
3
External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported.
4
ED = enhanced definition = 525p and 625p.
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
SD RGB Input Enable (0x87[7]) = 0
YCrCb
YCrCb
Y
CrCb
SD RGB Input Enable (0x87[7]) = 1
B
G
R
Y
CrCb
ED/HD Input Format (0x33[2]) = 0
YCrCb
ED/HD Input Format (0x33[2]) = 1
YCrCb
ED/HD Input Format (0x33[2]) = 0
YCrCb
ED/HD Input Format (0x33[2]) = 1
YCrCb
相關PDF資料
PDF描述
ADV7392BCPZ Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7392BCPZ-REEL Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7392EBZ Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7393 Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7393BCPZ Low Power, Chip Scale 10-Bit SD/HD Video Encoder
相關代理商/技術參數
參數描述
ADV7392BCPZ 制造商:Analog Devices 功能描述:
ADV7392BCPZ-3REEL 功能描述:Video Encoder IC DVD, Game Consoles, Media Players 40-LFCSP-WQ (6x6) 制造商:analog devices inc. 系列:- 包裝:帶卷(TR) 零件狀態:有效 類型:視頻編碼器 應用:DVD,游戲控制臺,媒體播放器 電壓 - 電源,模擬:2.6 V ~ 3.46 V 電壓 - 電源,數字:1.71 V ~ 1.89 V 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤,CSP 供應商器件封裝:40-LFCSP-WQ(6x6) 標準包裝:2,500
ADV7392BCPZ-REEL 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7392EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7392WBCPZ 制造商:Analog Devices 功能描述:
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