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參數資料
| 型號： | ADV7393BCPZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFSCP-40 |
| 文件頁數： | 26/96頁 |
| 文件大小： | 1209K |
| 代理商： | ADV7393BCPZ-REEL |
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ADV7390/ADV7391/ADV7392/ADV7393
Table 14. Register 0x01 to Register 0x09
SR7 to
SR0
Register
0x01
Mode Select
Register
Rev. 0 | Page 26 of 96
Bit Description
Reserved.
DDR Clock Edge Alignment.
Note: Only used for ED
1
and
HD DDR modes.
Bit Number
5
4
Register Setting
Chroma clocked in on rising clock edge and
luma clocked in on falling clock edge.
Reserved.
Reserved.
Luma clocked in on rising clock edge and
chroma clocked in on falling clock edge.
SD input.
ED/HD-SDR input
2
ED/HD-DDR input.
Reserved.
Reserved.
Reserved.
Reserved.
ED (at 54 MHz) input.
Zero must be written to these bits.
Disabled.
Enabled.
Disable manual RGB matrix adjust.
Enable manual RGB matrix adjust.
No sync.
Sync on all RGB outputs.
RGB component outputs.
YPrPb component outputs.
No sync output.
Output SD syncs on HSYNC and VSYNC pins.
No sync output.
Output ED/HD syncs on HSYNC and VSYNC
pins.
LSBs for GY.
Reset
Value
0x00
7
6
3
2
0
1
0
0
0
0
1
1
1
0
1
Reserved.
Input Mode.
Note: See Reg. 0x30, Bits[7:3]
for ED/HD format selection.
0
0
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
Reserved.
Reserved.
Test Pattern Black Bar.
3
0x20
Manual RGB Matrix Adjust.
Sync on RGB.
RGB/YPrPb Output Select.
SD Sync Output Enable.
0x02
Mode
Register 0
ED/HD Sync Output Enable.
0x03
ED/HD CSC
Matrix 0
ED/HD CSC
Matrix 1
x
x
0x03
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
LSBs for RV.
LSBs for BU.
LSBs for GV.
LSBs for GU.
Bits[9:2] for GY.
0xF0
0x04
0x05
ED/HD CSC
Matrix 2
ED/HD CSC
Matrix 3
ED/HD CSC
Matrix 4
ED/HD CSC
Matrix 5
ED/HD CSC
Matrix 6
0x4E
0x06
x
x
x
x
x
x
x
x
Bits[9:2] for GU.
0x0E
0x07
x
x
x
x
x
x
x
x
Bits[9:2] for GV.
0x24
0x08
x
x
x
x
x
x
x
x
Bits[9:2] for BU.
0x92
0x09
x
x
x
x
x
x
x
x
Bits[9:2] for RV.
0x7C
1
ED = enhanced definition = 525p and 625p.
2
Available on the ADV7392/ADV7393 (40-pin devices) only.
3
Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7393-DBRDZ | 功能描述:BOARD EVAL FOR ADV7393 RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:Advantiv® 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| ADV7393EBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7393WBCPZ | 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Trays |
| ADV7393WBCPZ-REEL | 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Tape and Reel |
| ADV73946603 | 制造商:LG Corporation 功能描述:Frame Assembly |
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