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參數資料
| 型號： | ADV7393BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFSCP-40 |
| 文件頁數： | 70/96頁 |
| 文件大小： | 1209K |
| 代理商： | ADV7393BCPZ |
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ADV7390/ADV7391/ADV7392/ADV7393
APPENDIX 3–SD CLOSED CAPTIONING
Subaddress 0x91 to Subaddress 0x94
The ADV739x supports closed captioning conforming to the
standard television synchronizing waveform for color
transmission. When enabled, closed captioning is transmitted
during the blanked active line time of Line 21 of the odd fields
and Line 284 of the even fields. Closed captioning can be
enabled using Subaddress 0x83, Bits[6:5].
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency and phase-locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by a Logic 1 start bit. Sixteen bits of data follow the start
bit. The data consists of two 8-bit bytes (seven data bits, and one
odd parity bit per byte). The data for these bytes is stored in SD
closed captioning registers (Subaddress 0x93 to Subaddress 0x94).
The ADV739x also supports the extended closed captioning
operation, which is active during even fields and encoded on
Line 284. The data for this operation is stored in SD closed
captioning registers (Subaddress 0x91 to Subaddress 0x92).
The ADV739x automatically generates all clock run-in signals
and timing that support closed captioning on Line 21 and Line 284.
Rev. 0 | Page 70 of 96
All pixels inputs are ignored on Line 21 and Line 284 if closed
captioning is enabled.
The FCC Code of Federal Regulations (CFR) Title 47 Section
15.119 and EIA-608 describe the closed captioning information
for Line 21 and Line 284.
The ADV739x uses a single buffering method. This means that
the closed captioning buffer is only 1-byte deep. Therefore,
there is no frame delay in outputting the closed captioning data
unlike other 2-byte deep buffering systems. The data must be
loaded one line before it is output on Line 21 and Line 284. A
typical implementation of this method is to use VSYNC to
interrupt a microprocessor, which in turn loads the new data
(2 bytes) in every field. If no new data is required for transmis-
sion, 0s must be inserted in both data registers; this is called
nulling. It is also important to load control codes, all of which
are double bytes, on Line 21. Otherwise, a TV does not recognize
them. If there is a message such as “Hello World” that has an
odd number of characters, it is important to add a blank
character at the end to make sure that the end-of-caption,
2-byte control code lands in the same field.
D0 TO D6
D0 TO D6
10.5 ± 0.25μs
12.91μs
7 CYCLES OF
0.5035MHz
CLOCK RUN-IN
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = F
= 3.579545MHz
AMPLITUDE = 40 IRE
10.003μs
50 IRE
40 IRE
27.382μs
33.764μs
BYTE 1
BYTE 0
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
S
T
A
R
T
P
A
R
I
T
Y
P
A
R
I
T
Y
0
Figure 101. SD Closed Captioning Waveform, NTSC
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| ADV7393BCPZ-REEL | 功能描述:IC DAC ENCODER VID HDTV 40-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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| ADV7393EBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
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