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參數資料
| 型號： | AG1170-S5 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | +5V / +3.3V Low Power Ringing SLIC |
| 中文描述： | 5V的/ 3.3V的低功率振鈴用戶接口 |
| 文件頁數： | 10/15頁 |
| 文件大小： | 362K |
| 代理商： | AG1170-S5 |
V1.9 September 2006
Data Sheet
Ag1170
+5V / +3.3V LOW POWER RINGING SLIC
8.0 Layout Considerations.
8.1 Power and Ground
Figure 7 gives an example of the tracking needed for
the Ag1170. Tracks to the +V
PWR
and GND
PWR
should
be made as thick as possible. To maximise the
performance of the device, signal tracks should be kept
as short as possible. A low impedance (ESR)
capacitor must be used for C2. To reduce DC/DC noise
capacitors up to 10nF may be connected to ground at
Tip and Ring.
PD is a sensitive node. Keep the tracking as short as
possible. Particularly if connecting a transistor to this
pin.
8.2 Impedance
ZT1, ZT2 and ZB are sensitive nodes. Keep the tracks
as short as possible.
8
1
Bottom View
7
9
RM
+V
A
codec
circuitry
25V (C3)
6.3V (C4)
20
Must be low ESR
21
circuitry
the input side of the power filter.
10R0
16V (C1)
GND
PWR
ZT2
GND
A
FILTER
(R1)
Pin Names
Tip (A)
Ring (B)
IC
PD
NC
NC
+V
PWR
+V
SHK
V
OUT
V
ZT1
to other
0.1uF,
100uF,
220uF, 10V (C2)
to other
Tracks for +V
and +V
, and for
GND
and GND
are joined at
0.1uF,
GND
PWR
ZB
POWER
Figure 7: Typical Layout
Silver Telecom 2006
10
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