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參數(shù)資料
| 型號(hào)： | AG1460 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | QUAD 5V RINGING SLIC |
| 中文描述： | 四5V的振鈴用戶接口 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大小： | 264K |
| 代理商： | AG1460 |
V1.4 May 2004
Data Sheet
Ag1460
QUAD 5V RINGING SLIC
The DC-DC converter can be switched off by applying
a logic 1 to the PD input. This reduces the current
consumption to a nominal 10mA. The SLIC takes
50ms to power up from this powered down state.
When using the power down state it is recommended
that the SLIC is polled (powered up periodically) to
check for SHK (the subscriber has gone off hook).
Since the DC-DC converter supplies the power to all
four SLICs on the Ag1460, all four SLICs will be
powered down when the PD signal is applied.
2.0 The 2-4 Wire (hybrid) Conversion.
Each individual SLIC of the Ag1460 transmits and
receives balanced 2-wire analog signals at the Tip and
Ring connections. These are converted to a ground
referenced output at V
OUT
and from a ground referenced
input at V
IN
.
V
OUT
and V
IN
are normally connected to a Codec for
conversion to and from a digital Pulse Code Modulated
(PCM) stream.
2.1 The 2 Wire Impedance.
For the Ag1460, the input impedance, Zin, of each
SLIC is set to 600
. For countries where the line
impedance is 600
e.g. North America, no external
adjustment is required. For countries where an
alternative line impedance is used the Codec filter
characteristics can be programmed to give the required
matching.
switches to produce a battery voltage of -72V. This will
produce greater than 40V
RMS
into a REN of 3. The
slope of the edges on the ringing waveform is
determined by the value of the slew rate capacitor
connected between the CAP pin and Ground. A 220nF
capacitor is recommended with 20Hz ringing.
When the “off-hook” condition occurs during ringing,
the ring-trip circuit on the Ag1460 senses the loop
current flowing and signals the off-hook condition on
the SHK output (as shown in figure 3). The SHK signal
must be “debounced” to remove any spurious pulses
by the controlling processor. On detection of SHK the
ringing signal must be removed from the F/R pin and
RM taken to a logic 0 within 500ms to avoid excessive
power dissipation in the line driver circuit. The ring-trip
function will operate up to a maximum loop resistance
of 800
(including telephone), which corresponds to
around 3km loop length.
To keep within the power rating of the on-board DC-DC
converter, it is important that only one SLIC channel is
ringing at any time. This can be met by using a ringing
cadence of 1 second ON, 3 seconds OFF. The active
ringing channel is then sequenced so that all four SLIC
channels may be in the ringing mode, but only one is
supplying ringing current at any one time.
1.3 Loop Off and Power Down
The loop current can be removed from the line by
switching the LO input to a logic 1. This can be used
as a power denial to the line or to present a very high
impedance to the line. Typically used when carrying
out maintenance on the line, or to suspend service
during a line fault, etc.
Country
USA
Germany
Spain
South Africa
Europe
CTR21
UK
Termination
Impedance
600R
220R
820R
120nF
270R
750R
150nF
300R
1000R
220nF
Balance
Impedance
600R
220R
820R
120nF
270R
750R
150nF
310nF
370R
620R
56K
200K
470pF
68K
180K
620pF
75K
240K
910pF
Z
T
150K
Z
B
150K
150K
100pF
150K
150K
100pF
150K
150K
100pF
TBD
TBD
TBD
TBD
Table 1: Impedance Programming for Ag1460P
Silver Telecom 2004
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AG1460D | QUAD 5V RINGING SLIC |
| AG1460PD | QUAD 5V RINGING SLIC |
| AG1460PS | QUAD 5V RINGING SLIC |
| AG1460S | QUAD 5V RINGING SLIC |
| AG2120 | FULLY FEATURED PSTN INTERFACE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AG1460D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:QUAD 5V RINGING SLIC |
| AG1460PD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:QUAD 5V RINGING SLIC |
| AG1460PS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:QUAD 5V RINGING SLIC |
| AG1460S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:QUAD 5V RINGING SLIC |
| AG15 | 制造商:Ferraz Shawmut 功能描述: |
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