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參數資料
| 型號： | AM27C128-200DIB |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | Triple 3-input positive-NOR gates 14-SO 0 to 70 |
| 中文描述： | 16K X 8 UVPROM, 200 ns, CDIP28 |
| 封裝： | WINDOWED, CERAMIC, DIP-28 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 171K |
| 代理商： | AM27C128-200DIB |
FINAL
Publication#
11420
Issue Date:
May 1998
Rev:
E
Amendment/
0
Am27C128
128 Kilobit (16 K x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
I
Fast access time
— Speed options as fast as 45 ns
I
Low power consumption
— 20 μA typical CMOS standby current
I
JEDEC-approved pinout
I
Single +5 V power supply
I
±
10% power supply tolerance standard
I
100% Flashrite programming
— Typical programming time of 2 seconds
I
Latch-up protected to 100 mA from –1 V to
V
CC
+ 1 V
I
High noise immunity
I
Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
I
Standard 28-pin DIP, PDIP, and 32-pin PLCC
packages
GENERAL DESCRIPTION
The Am27C128 is a 128-Kbit, ultraviolet erasable pro-
grammable read-only memory. It is organized as 16
Kwords by 8 bits per word, operates from a single +5 V
supply, has a static standby mode, and features fast
single address location programming. Products are
available in windowed ceramic DIP packages, as well
as plastic one time programmable (OTP) PDIP and
PLCC packages.
Data can be typically accessed in less than 45 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating bus contention in a multiple bus micro-
processor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 80 mW in active mode, and
100 μW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 μs pulses), re-
sulting in a typical programming time of 2 seconds.
BLOCK DIAGRAM
11420E-1
A0–A13
Address
Inputs
PGM#
CE#
OE#
V
CC
V
SS
V
PP
Data Outputs
DQ0–DQ7
Output
Buffers
Y
Gating
131,072
Bit Cell
Matrix
X
Decoder
Y
Decoder
Output Enable
Chip Enable
and
Prog Logic
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