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參數(shù)資料
| 型號： | Am27C2048-70DI5B |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 2 Megabit (128 K x 16-Bit) CMOS EPROM |
| 中文描述： | 2兆位（128畝× 16位）的CMOS存儲器 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 173K |
| 代理商： | AM27C2048-70DI5B |
FINAL
Publication#
11407
Issue Date:
May 1998
Rev:
G
Amendment/
0
Am27C2048
2 Megabit (128 K x 16-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
I
Fast access time
— Speed options as fast as 55 ns
I
Low power consumption
— 100 μA maximum CMOS standby current
I
JEDEC-approved pinout
— Plug-in upgrade of 1 Mbit EPROM
— 40-pin DIP/PDIP
— 44-pin PLCC
I
Single +5 V power supply
I
±
10% power supply tolerance standard
I
100% Flashrite programming
— Typical programming time of 16 seconds
I
Latch-up protected to 100 mA from –1 V to
V
CC
+ 1 V
I
Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
I
High noise immunity
GENERAL DESCRIPTION
The Am27C2048 is a 2 Mbit, ultraviolet erasable pro-
grammable read-only memory. It is organized as 128 K
words, operates from a single +5 V supply, has a static
standby mode, and features fast single address loca-
tion programming. The Am27C2048 is ideal for use in
16-bit microprocessor systems. The device is available
in windowed ceramic DIP packages, and plastic one
time programmable (OTP) PDIP and PLCC packages.
Data can be typically accessed in less than 55 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating bus contention in a multiple bus micro-
processor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 125 mW in active mode,
and 100 μW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 μs pulses), re-
sulting in a typical programming time of 16 seconds.
BLOCK DIAGRAM
11407G-1
A0–A16
Address
Inputs
PGM#
CE#
OE#
V
CC
V
SS
V
PP
Data Outputs
DQ0–DQ15
Output
Buffers
Y
Gating
2,097,152
Bit Cell
Matrix
X
Decoder
Y
Decoder
Output Enable
Chip Enable
and
Prog Logic
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