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參數資料
| 型號： | AM27C4096-255DIB |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | Quad 2-input positive-NAND buffers 14-PDIP 0 to 70 |
| 中文描述： | 256K X 16 UVPROM, 250 ns, CDIP40 |
| 封裝： | WINDOWED, CERAMIC, DIP-40 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 165K |
| 代理商： | AM27C4096-255DIB |
FINAL
Publication#
11408
Issue Date:
May 1998
Rev:
F
Amendment/
0
Am27C4096
4 Megabit (256 K x 16-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
I
Fast access time
— Speed options as fast as 90 ns
I
Low power consumption
— 100 μA maximum CMOS standby current
I
JEDEC-approved pinout
— Plug-in upgrade of 1 Mbit and 2 Mbit EPROMs
— 40-pin DIP/PDIP
— 44-pin PLCC
I
Single +5 V power supply
I
±
10% power supply tolerance standard
I
100% Flashrite programming
— Typical programming time of 32 seconds
I
Latch-up protected to 100 mA from –1 V to
V
CC
+ 1 V
I
High noise immunity
GENERAL DESCRIPTION
The Am27C4096 is a 4 Mbit, ultraviolet erasable pro-
grammable read-only memory. It is organized as 256
Kwords, operates from a single +5 V supply, has a
static standby mode, and features fast single address
location programming. The Am27C4096 is ideal for use
in 16-bit microprocessor systems. The device is avail-
able in windowed ceramic DIP packages, and plastic
one time programmable (OTP) PDIP and PLCC pack-
ages.
Data can be typically accessed in less than 90 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating bus contention in a multiple bus micro-
processor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 125 mW in active mode,
and 125 μW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 μs pulses), re-
sulting in a typical programming time of 32 seconds.
BLOCK DIAGRAM
11408F-1
A0–A17
Address
Inputs
CE#/PGM#
OE#
V
CC
V
SS
V
PP
Data Outputs
DQ0–DQ15
Output
Buffers
Y
Gating
4,194,304
Bit Cell
Matrix
X
Decoder
Y
Decoder
Output Enable
Chip Enable
and
Prog Logic
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