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參數資料
| 型號： | AM27X128-70PI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | CMOS Quad 2-Input NAND Schmitt Triggers 14-CDIP -55 to 125 |
| 中文描述： | 16K X 8 OTPROM, 70 ns, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 139K |
| 代理商： | AM27X128-70PI |
FINAL
Publication#
12083
Issue Date:
May 1998
Rev:
F
Amendment/
0
Am27X128
128 Kilobit (16 K x 8-Bit) CMOS ExpressROM Device
DISTINCTIVE CHARACTERISTICS
I
As an OTP EPROM alternative:
— Factory optimized programming
— Fully tested and guaranteed
I
As a Mask ROM alternative:
— Shorter leadtime
— Lower volume per code
I
Fast access time
— 55 ns
I
Single +5 V power supply
I
Compatible with JEDEC-approved EPROM
pinout
I
±
10% power supply tolerance
I
High noise immunity
I
Low power dissipation
— 100 μA maximum CMOS standby current
I
Available in Plastic Dual-In-line Package (PDIP)
and Plastic Leaded Chip Carrier (PLCC)
I
Latch-up protected to 100 mA from –1 V to
V
CC
+ 1 V
I
Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
GENERAL DESCRIPTION
The Am27X128 is a factory programmed and tested
OTP EPROM. It is programmed after packaging prior to
final test. Every device is rigorously tested under AC
and DC operating conditions to your stable code. It is
organized as 16 Kwords by 8 bits per word and is avail-
able in plastic dual in-line packages (PDIP), as well as
plastic leaded chip carrier (PLCC) packages. Express-
ROM devices provide a board-ready memory solution
for medium to high volume codes with short leadtimes.
This offers manufacturers a cost-effective and flexible
alternative to OTP EPROMs and mask programmed
ROMs.
Data can be accessed as fast as 55 ns, allowing
high-performance microprocessors to operate with re-
duced WAIT states. The device offers separate Output
Enable (OE#) and Chip Enable (CE#) controls, thus
eliminating bus contention in a multiple bus micropro-
cessor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 80 mW in active mode, and
100 μW in standby mode.
BLOCK DIAGRAM
12083F-1
A0–A13
Address
Inputs
CE#
OE#
V
CC
V
SS
Data Outputs DQ0–DQ7
Output
Buffers
Y
Gating
131,072
Bit Cell
Matrix
X
Decoder
Y
Decoder
Output Enable
Chip Enable
and
Prog Logic
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