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參數資料
| 型號： | AM29BDS323D |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 32兆位（2米× 16位）的CMOS 1.8伏，只有同時讀/寫，突發模式閃存 |
| 文件頁數： | 1/44頁 |
| 文件大小： | 746K |
| 代理商： | AM29BDS323D |
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PRELIMINARY
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
23476
Issue Date:
September 4, 2001
Rev:
B
Amendment/
+4
Refer to AMD’s Website (www.amd.com) for the latest information.
Am29BDS323D
32 Megabit (2 M x 16-Bit)
CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
DISTINCTIVE CHARACTERISTICS
I
Single 1.8 volt read, program and erase (1.7 to
1.9 volt)
I
Multiplexed Data and Address for reduced I/O
count
—
A0
–
A15 multiplexed as D0
–
D15
—
Addresses are latched with AVD# control inputs
while CE# low
I
Simultaneous Read/Write operation
—
Data can be continuously read from one bank
while executing erase/program functions in other
bank
—
Zero latency between read and write operations
I
Read access times at 40 MHz
—
Burst access times of 20 ns @ 30 pF
at industrial temperature range
—
Asynchronous random access times
of 110 ns @ 30 pF
—
Synchronous random access times
of 120 ns @ 30 pF
I
Burst length
—
Continuous linear burst
I
Power dissipation (typical values, 8 bits
switching, C
L
= 30 pF)
—
Burst Mode Read: 25 mA
—
Simultaneous Operation: 40 mA
—
Program/Erase: 15 mA
—
Standby mode: 0.2 μA
I
Sector Architecture
—
Eight 4 Kword sectors and sixty-three sectors of
32 Kwords each
—
Bank A contains the eight 4 Kword sectors and
fifteen 32 Kword sectors
—
Bank B contains forty-eight 32 Kword sectors
I
Sector Protection
—
Software command sector locking
—
WP# protects the last two boot sectors
—
All sectors locked when V
PP
= V
IL
I
Software command set compatible with JEDEC
42.4 standards
—
Backwards compatible with Am29F and Am29LV
families
I
Minimum 1 million erase cycle guarantee
per sector
I
20-year data retention at 125
°
C
—
Reliable operation for the life of the system
I
Embedded Algorithms
—
Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
—
Embedded Program algorithm automatically
writes and verifies data at specified addresses
I
Data# Polling and toggle bits
—
Provides a software method of detecting
program and erase operation completion
I
Erase Suspend/Resume
—
Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
I
Hardware reset input (RESET#)
—
Hardware method to reset the device for reading
array data
I
CMOS compatible inputs, CMOS compatible
outputs
I
Low V
CC
write inhibit
I
Package Option
—
47-ball FBGA
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