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參數資料
| 型號： | AM29LV200BT-70RSC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 256K X 8 FLASH 3V PROM, 70 ns, PDSO44 |
| 封裝： | MO-180AA, SOP-44 |
| 文件頁數： | 1/41頁 |
| 文件大小： | 843K |
| 代理商： | AM29LV200BT-70RSC |
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This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21521
Rev: D Amendment/0
Issue Date: November 18, 1999
Am29LV200B
2 Megabit (256 K x 8-Bit/128 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation
— 2.7 to 3.6 volt read and write operations for
battery-powered applications
s Manufactured on 0.32 m process technology
— Compatible with 0.5 m Am29LV200 device
s High performance
— Full voltage range: access times as fast as 70 ns
— Regulated voltage range: access times as fast as
55 ns
s Ultra low power consumption (typical values at
5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
s Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
three 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
s Top or bottom boot block configurations
available
s Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
s Minimum 1,000,000 write cycle guarantee per
sector
s 20-year data retention at 125
°C
— Reliable operation for the life of the system
s Package option
— 48-pin TSOP
— 44-pin SO
s Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
s Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
s Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
s Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
s Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
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