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參數資料
型號: AM29SL800BB200EI
廠商: ADVANCED MICRO DEVICES INC
元件分類: PROM
英文描述: 8-Bit Identity/Magnitude Comparators (P=Q) with Enable 20-CDIP -55 to 125
中文描述: 1M X 8 FLASH 1.8V PROM, 200 ns, PDSO48
封裝: TSOP-48
文件頁數: 1/41頁
文件大?。?/td> 543K
代理商: AM29SL800BB200EI
ADVANCE INFORMATION
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
Publication#
21545
Issue Date:
March 1998
Rev:
A
Amendment/
+2
Am29SL800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 1.8 Volt-only Super Low Voltage Flash Memory
DISTINCTIVE CHARACTERISTICS
I
Single power supply operation
— 1.8 to 2.2 V for read, program, and erase
operations
— Ideal for battery-powered applications
I
Manufactured on 0.35 μm process technology
I
High performance
— Access times as fast as 170 ns
I
Ultra low power consumption (typical values at
5 MHz)
— 65 nA Automatic Sleep Mode current
— 65 nA standby mode current
— 5 mA read current
— 10 mA program/erase current
I
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
I
Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
I
Top or bottom boot block configurations
available
I
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
I
Minimum 1,000,000 write cycle guarantee per
sector
I
Package option
— 48-pin TSOP
— 48-ball FBGA
I
Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
I
Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
I
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
I
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
I
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
相關PDF資料
PDF描述
Am29SL800BB200EIB High Speed CMOS Logic Dual Positive-Edge Trigger D Flip-Flops with Set and Reset 14-CDIP -55 to 125
AM29SL800BB200FC 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
Am29SL800BB200FCB High Speed CMOS Logic Dual Positive-Edge Trigger D Flip-Flops with Set and Reset 14-CDIP -55 to 125
AM29SL800BB200FI High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latch 16-CDIP -55 to 125
Am29SL800BB200FIB 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
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