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參數資料
| 型號： | AMP374P6453BT1-C1H |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs |
| 中文描述： | 64米× 72 SDRAM的內存32兆的基礎上× 8，4銀行，8K的刷新，3.3同步DRAM，帶ECC |
| 文件頁數： | 3/12頁 |
| 文件大小： | 72K |
| 代理商： | AMP374P6453BT1-C1H |
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 3 of 12
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
PIN CONFIGURATION DESCRIPTION
Pin
Name
Input Function
CLK
System Clock
Active on the positive going edge to sample all inputs.
CS
Chip Select
Disables or enables device operation by masking or enabling all inputs
except CLK, CKE, and DQM.
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least one cycle prior to new command. Disable
input buffers for power down in standby.
CKE should be enabled 1CLK+t ss prior to valid command.
CKE
Clock Enable
A0 - A12
Address
Row/Column addresses are multiplexed on the same pins.
Row Address: RA0
–
RA12, Column address: CA0
–
CA9
BA0 - BA1
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS
low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
low.
Enables column access.
CAS
Column Address Strobe
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from
CAS
,
WE
active.
DQM0 - DQM7
Data Input/Output Mask
Makes data output Hi-Z,
tSHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte Masking)
Data inputs/outputs are multiplexed on the same pins.
DQ0 - DQ63
Data Input/Output
CB0 - 7
Check bit
Check bits for ECC.
WP
Write Protect
WP pin is connected to Vss through 47K
Resistor. When WP is
“
high
”
EEPROM programming will be inhibited, and the entire memory will be
write-protected.
Power and ground for the input buffers and the core logic.
V
DD
/Vss
Power Supply/Ground
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