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參數資料
| 型號： | AMP374P6453BT1-C1HS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs |
| 中文描述： | 64米× 72 SDRAM的內存32兆的基礎上× 8，4銀行，8K的刷新，3.3同步DRAM，帶ECC |
| 文件頁數： | 5/12頁 |
| 文件大小： | 72K |
| 代理商： | AMP374P6453BT1-C1HS |
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 5 of 12
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted) T A = 0 to 70
o
C
Symbol
Test Condition
Version
-1H
Unit
ICC1*
Burst Length = 1
t
RC
≥
t
RC
(min)
I
OL
= 0mA
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min),
CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min),
CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
OL
= 0mA
Page Burst
4 Banks activated
t
CCD
= 2CLK
S
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
1,260
mA
ICC2P
ICC2PS
ICC2N
36
36
mA
288
mA
ICC2NS
252
108
108
ICC3P
ICC3PS
ICC3N
mA
540
mA
ICC3NS
450
ICC4
mA
1,305
ICC5
ICC6
2,070
90
mA
mA
ICC1:
ICC2P:
ICC2PS:
ICC2N:
ICC2NS:
ICC3P:
ICC3PS:
ICC3N:
ICC3NS:
ICC4:
ICC5
ICC6:
Operating Current (one bank active)
Precharge Standby Current in power-down mode
Precharge Standby Current in power-down mode.
Precharge Standby Current in non power-down mode.
Precharge Standby Current in non power-down mode.
Active Standby Current in power-down mode.
Active Standby Current in power-down mode.
Active Standby Current in non power-down mode (One Bank Active).
Active Standby Current in non power-down mode (One Bank Active).
Operating Current (Burst Mode)
Refresh Current
Self Refresh Current
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
).
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