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參數資料
| 型號： | AMP374P6453BT1C1H |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs |
| 中文描述： | 64米× 72 SDRAM的內存32兆的基礎上× 8，4銀行，8K的刷新，3.3同步DRAM，帶ECC |
| 文件頁數： | 8/12頁 |
| 文件大小： | 72K |
| 代理商： | AMP374P6453BT1C1H |
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 8 of 12
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
SIMPLIFIED TRUTH TABLE
COMMAND
Register
CKEn-1
H
H
CKEn
X
H
L
H
CS
L
L
RAS
L
L
CAS WE
L
L
DQM
X
X
B0,1 A10/AP A12-11,A9-0 Note
OP CODE
Mode Register Set
Auto Refresh
Self Entry
Refresh Exit
L
H
1, 2
3
3
3
3
X
Refresh
L
L
H
L
H
X
L
H
X
H
H
X
H
X
X
Bank Active & Row Address
Read &
Auto Precharge Disable
Column Address
Auto Precharge Enable
H
H
X
X
V
Row Address
L
H
(A0-A9)
L
H
(A0-A9)
X
L
H
Column
4
4, 5
X
L
H
L
H
X
V
Address
Write &
Column Address
Auto Precharge Enable
Auto Precharge Disable
Column
4
4, 5
H
X
L
H
L
L
X
V
Address
Burst Stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
6
Bank Selection
All Banks
V
X
Clock Suspend or Entry
Active Power Down
H
L
H
L
X
H
L
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H X
X
X
V
V
X
X
H
X
X
L
H
H
L
X
X
Precharge Power Down Entry
Mode
Exit
L
H
DQM
No Operation Command
H
H
X
X
7
X
H
L
X
H
X
Exit
(V = Valid, X = Don
’
t Care, H = Logic High, L = Logic Low)
Note:
1.
OP Code: Operand Code
A0 - A12, BA0 - BA1: Program keys. (@MRS)
MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
Auto refresh functions are same as CBR refresh of DRAM.
The automatic precharge without row precharge command is meant by
“
Auto
”
.
Auto/self refresh can be issued only at all banks precharge state.
BA0 - BA1: Bank select addresses.
If both BA0 and BA1 are
“
Low
”
at read, write, row active and precharge, bank A is selected.
If both BA0 is
“
Low
”
and BA1 is
“
High
”
at read, write, row active and precharge, bank B is selected.
If both BA0 is
“
High
”
and BA1 is
“
Low
”
at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are
“
High
”
at read, write, row active and precharge, bank D is selected.
If A10/AP is
“
High
”
at row precharge, BA0 and BA1 are ignored and all banks are selected.
During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
Burst stop command is valid at every burst length.
DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
2.
3.
4.
5.
6.
7.
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| AMP374P6453BT1-C1HS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs |
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