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參數(shù)資料
| 型號： | AMPAL22V10 |
| 廠商： | Advanced Micro Devices, Inc. |
| 元件分類： | PAL |
| 英文描述： | PAL22V10 Family, AmPAL22V10/A 24-Pin TTL Versatile PAL Device |
| 中文描述： | PAL22V10家庭，AmPAL22V10 / 24針的TTL多功能PAL制式設(shè)備 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大小： | 184K |
| 代理商： | AMPAL22V10 |
Publication#
16559
Issue Date:
February 1996
Rev.
C
Amendment
/0
2-197
Advanced
Micro
Devices
PAL22V10 Family, AmPAL22V10/A
24-Pin TTL Versatile PAL Device
FINAL
COM’L: -7/10/15
DISTINCTIVE CHARACTERISTICS
I
As fast as 7.5-ns propagation delay and
91 MHz f
MAX
(external)
I
10 Macrocells programmable as registered or
combinatorial, and active high or active low to
match application needs
I
Varied product term distribution allows up to
16 product terms per output for complex
functions
I
Global asynchronous reset and synchronous
preset for initialization
I
Power-up reset for initialization and register
preload for testability
I
Extensive third-party software and programmer
support through FusionPLD partners
I
24-Pin SKINNYDIP, 24-pin Flatpack and
28-pin PLCC and LCC packages save space
GENERAL DESCRIPTION
The PAL22V10 provides user-programmable logic for
replacing conventional SSI/MSI gates and flip-flops at a
reduced chip count.
The PAL22V10 device implements the familiar Boolean
logic transfer function, the sum of products. The PAL de-
vice is a programmable AND array driving a fixed OR
array. The AND array is programmed to create custom
product terms, while the OR array sums selected terms
at the outputs.
The product terms are connected to the fixed OR array
with a varied distribution from 8 to 16 across the outputs
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be pro-
grammed as registered or combinatorial, and active
high or active low. The output configuration is
determined by two fuses controlling two multiplexers in
each macrocell.
AMD’s FusionPLD program allows PAL22V10 designs
to be implemented using a wide variety of popular indus-
try-standard design tools. By working closely with the
FusionPLD partners, AMD certifies that the tools pro-
vide accurate, quality support. By ensuring that third-
party tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar.
BLOCK DIAGRAM
OLOGIC
CELL
OLOGIC
CELL
OLOGIC
CELL
OLOGIC
CELL
OLOGIC
CELL
OLOGIC
CELL
OLOGIC
CELL
OLOGIC
CELL
OLOGIC
CELL
OLOGIC
CELL
RESET
PRESET
Programmable
AND Array
(44 x 132)
CLK/I
0
1
I
1
- I
11
11
8
10
12
14
16
16
14
12
10
8
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
16559C-1
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