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參數資料
| 型號： | AN221E04-QFPTR |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Dynamically Reconfigurable FPAA With Enhanced I/O |
| 中文描述： | 動態可重構FPAA的具有增強的I / O |
| 文件頁數： | 4/21頁 |
| 文件大小： | 448K |
| 代理商： | AN221E04-QFPTR |
AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
DS030100-U006a
- 4 -
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
AVDD(2)
BVDD
DVDD
Min
Typ
Max
Unit
Comment
DC Power Supplies
-0.5
-
5.5 V
V
AVSS, BVSS, DVSS and SVSS all
held to 0.0 V
xVDD to xVDD Offset
-0.5
0.5
V
Ideally all supplies should be at the
same voltage
Still air, No heatsink, 4 layer board,
44 pins.
θ
ja = 55°C/W
Package Power Dissipation
Pmax 25°C
Pmax 85°C
Vinmax
Top
Tstg
-
-
1.8
0.73
Vdd+0.5
85
150
W
Analog and Digital Input Voltage
Ambient Operating Temperature
Storage Temperature
Vss-0.5
-40
-65
-
-
V
°C
°C
a
Absolute Maximum DC Power Supply Rating - The failure mode is non-catastrophic for Vdd of up to 7 volts, but will cause reduced
operating life time. The additional stress caused by higher local electric fields within the CMOS circuitry may induce metal migration,
oxide leakage and other time/quality related issues.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Comment
DC Power Supplies
AVDD(2)
BVDD
DVDD
4.75
5.00
5.25
V
AVSS, BVSS, DVSS and SVSS all
held to 0 V
Analog Input Voltage.
Vina
VMR-1.9
-
VMR+1.9
V
VMR is 2.0 volts above AVSS
Digital Input Voltage
Junction Temp
Vind
Tj
0
-
-
DVDD
125
V
°C
Assume a package
θ
ja = 55°C/W
b
-40
b
In order to calculate the junction temperature you must first empirically determine the current draw (total Idd) for the design. Once the
current consumption established then the following formula can be used; Tj = Ta + Idd x Vdd x 55 °C/W, where Ta is the ambient
temperature. The worst case
θ
ja of 55 °C/W assumes no air flow and no additional heatsink of any type.
General Digital I/O Characteristics (Vdd = 5v +/- 10%, -40 to 85 deg.C)
Parameter
Symbol
Input Voltage Low
Vih
Input Voltage High
Vil
Output Voltage Low
Vol
Output Voltage High
Voh
Input Leakage Current
Iil
Input Leakage Current
Iil
Min
0
70
0
80
-
Typ
-
-
-
-
-
Max
30
100
20
100
±1.0
Unit
-
-
-
-
μA
Comment
% of DVDD
% of DVDD
% of DVDD
% of DVDD
All pins except DCLK
DCLK if a crystal is connected and
the on-chip oscillator is used
The maximum load for a digital
output is 10 pF // 10 Kohm
The maximum load for a digital
output is 10 pF // 10 Kohm
For MODE = 1, Max DCLK is
16 MHz
Divide down to <8 MHz prior to use
as a CAB clock
All clocks
-
±12.0
-
μA
Max. Capacitive Load
Cmax
-
-
10
pF
Min. Resistive Load
Rmin
10
-
-
Kohm
DCLK Frequency
Fmax
-
-
40
MHz
ACLK Frequency
Fmax
-
-
40
MHz
Clock Duty Cycle
-
45
-
55
%
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