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參數(shù)資料
| 型號： | AN231E04-E2-QFNSP |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Dynamically Reconfigurable dpASP |
| 中文描述： | 動態(tài)可重構(gòu)dpASP |
| 文件頁數(shù)： | 19/24頁 |
| 文件大小： | 445K |
| 代理商： | AN231E04-E2-QFNSP |
AN231E04 Datasheet – Dynamically Reconfigurable dpASP
DS231000-U001d
- 19 -
PINOUT
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Pin
Name
I1P
I1N
O1N
O1P
AVSS
O2P
O2N
I2N
I2P
AVDD
I3P
I3N
O3N
O3P
IO5P
IO5N
IO6P
IO6N
IO7P
IO7N
O4P
O4N
I4N
I4P
BVDD
VREFP
VMR
VREFN
BVSS
CFGFLGb
Pin
Type
+ve Input
-ve Input
-ve Output
+ve Output
Ground Supply
+ve Input
-ve Input
-ve Output
+ve Output
Positive Supply
+ve Input
-ve Input
-ve Output
+ve Output
+ve Input/Output
-ve Input/Output
+ve Input/Output
-ve Input/Output
+ve Input/Output
-ve Input/Output
+ve Input
-ve Input
-ve Output
+ve Output
Positive Supply
Reference load
Reference load
Reference load
Ground Supply
Digital Output
Comments
Type1 Input/Output cell. (IO Cell 1)
Analog or digital input and output pins
Analog ground, 0 Volts
Type1 Input/Output cell. (IO cell 2)
Analog or digital input and output pins
Analog power 3.3 Volts
Type1a Input/Output cell. (IO cell 3)
Analog or digital input and output pins
Type 2 Input/Output cell. (IO cell 5)
Type 2 Input/Output cell. (IO cell 6)
Type 2a Input/Output cell. (IO cell 7)
Type1a Input/Output cell. (IO cell 3)
Analog or digital input and output pins
Voltage reference power 3.3 Volts
Reference Voltage Noise suppression. Connected a 100nF capacitor from each pin
to BVSS. The capacitive reservoir is used to sink and source peak current, thus
reducing noise and maintaining stable reference voltages.
Voltage reference ground 0 Volts
Config status pin. Open Drain Output with optional internal Pull-up resistor. The
output voltage is also sensed by internal circuitry, See figure XX for schematic.
Chip select pin
Device select
CMOS, configuration logic strobe clock.
CMOS, Analog clock input
Connect to VSS (ACLK and SCLK sourced externally).
Connect to VDD (ACLK sourced externally, MEMCLK & SO generated internally).
Digital power 3.3 Volts
Digital ground 0.0 Volts
CMOS Serial data input.
CMOS. Default function, Indicates Local Configuration Complete.
Optional function (Single dpASP designs only), pin can be configured as user
assignable signal path digital output under software control.
Error indication.
Open Drain, External Pull-up resistor must be used (10KOhms) See fig XXa
Indicates Device activation. Open Drain Output with optional internal Pull-up resistor.
The output voltage is also sensed by internal circuitry, See figure XX for schematic.
Outputs MEMCLK clock when MODE pin = VSS.
Caution - Do not load this pin during reset (NOT to be pulled low externally)
Serial Out, ONLY used as an output for SPI-PROM setup bytes during configuration.
Connected to VSS to reset the dpASP. If held low the dpASP will remain in reset
(2msec delay internal set-up time follows release of RESETb (when this pin is pulled
high))
31
32
33
34
35
CS2b
CS1b
SCLK
ACLK
MODE
Digital input
Digital input
Digital input
Digital input
Digital input
36
37
38
39
DVDD
DVSS
SI
LCCb/
DOUT1
Positive Supply
Ground Supply
Digital input
Digital output
40
ERRb
Digital output
41
ACTIVATE Digital Output
42
MEMCLK/
DOUT2
SO
RESETb
Digital Output
43
44
Digital Output
Digital Input
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