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參數資料
| 型號： | AS5C512K8ECJ-17 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 512K x 8 SRAM HIGH SPEED SRAM with REVOLUTIONARY PINOUT |
| 中文描述： | 為512k × 8的SRAM高速SRAM和革命引腳排列 |
| 文件頁數： | 5/16頁 |
| 文件大小： | 416K |
| 代理商： | AS5C512K8ECJ-17 |
SRAM
AS5C512K8
Austin Semiconductor, Inc.
AS5C512K8
Rev. 4.5 7/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
167 ohms
167 ohms
1.73V
1.73V
C=5pF
C=30pF
Q
Q
Input pulse levels ...................................................... Vss to 3.0V
Input rise and fall times ......................................................... 3ns
Input timing reference levels ............................................... 1.5V
Output reference levels ........................................................ 1.5V
Output load ................................................. See Figures 1 and 2
NOTES
1.
All voltages referenced to V
SS
(GND).
2.
-2V for pulse width < 20ns
3.
I
is dependent on output loading and cycle rates.
4.
This parameter is guaranteed but not tested.
5.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6.
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV from steady state voltage.
7.
At any given temperature and voltage condition,
t
HZCE is less than
t
LZCE, and
t
HZWE is less than
t
LZWE.
8.
WE\ is HIGH for READ cycle.
t
LZCE,
t
LZWE,
t
LZOE,
t
HZCE,
t
HZOE and
t
HZWE
9.
Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11.
12. Chip enable and write enable can initiate and
terminate a WRITE cycle.
13. Output enable (OE\) is inactive (HIGH).
14. Output enable (OE\) is active (LOW).
15. ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150°C. Care should be taken to limit power to
acceptable levels.
t
RC = Read Cycle Time.
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
DATA RETENTION ELECTRICAL CHARACTERISTICS
(L Version Only)
DESCRIPTION
CONDITIONS
CE\ > V
CC
-0.2V
V
IN
> V
CC
-0.2 or 0.2V
AC TEST CONDITIONS
SYM
MIN
MAX
UNITS
NOTES
Vcc for Retention Data
V
DR
2
V
Data Retention Current
Vcc = 2.0V
I
CCDR
t
CDR
t
R
4.5
mA
Chip Deselect to Data
0
ns
4
Operation Recovery Time
10
ms
4, 11
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相關代理商/技術參數 |
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| AS5C512K8ECJ-17/883C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| AS5C512K8ECJ-17/H | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:512K x 8 SRAM HIGH SPEED SRAM with REVOLUTIONARY PINOUT |
| AS5C512K8ECJ-17/IT | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:512K x 8 SRAM HIGH SPEED SRAM with REVOLUTIONARY PINOUT |
| AS5C512K8ECJ-17/XT | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:512K x 8 SRAM HIGH SPEED SRAM with REVOLUTIONARY PINOUT |
| AS5C512K8ECJ-17E/883C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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