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參數(shù)資料
| 型號： | AS7C33512PFS32A-225TQC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 32 STANDARD SRAM, 6.9 ns, PQFP100 |
| 封裝： | 14 X 20 MM, TQFP-100 |
| 文件頁數(shù)： | 1/21頁 |
| 文件大?。?/td> | 463K |
| 代理商： | AS7C33512PFS32A-225TQC |
December 2002
Advance Information
Copyright Alliance Semiconductor. All rights reserved.
AS7C33512PFS32A
AS7C33512PFS36A
12/2/02, v. 0.9.8 Advance Info
Alliance Semiconductor
1 of 21
3.3V 512K
× 32/36 pipelined burst synchronous SRAM
Features
Organization: 524,288 words × 32 or 36 bits
Fast clock speeds to 250MHz in LVTTL/LVCMOS
Fast clock to data access: 2.6/2.8/3/3.4 ns
Fast OE access time: 2.6/2.8/3/3.4 ns
Fully synchronous register-to-register operation
Single register flow-through mode
Single-cycle deselect
- Dual-cycle deselect also available (AS7C331MPFD18A,
AS7C33512PFD32A/ AS7C33512PFD36A)
Asynchronous output enable control
Available in 100-pin TQFP package and 165-ball BGA
Individual byte write and global write
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate VDDQ
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Boundary scan using IEEE 1149.1 JTAG function
NTD1 pipelined architecture available
(AS7C331MNTD18A, AS7C33512NTD32A/
AS7C33512NTD36A)
1 NTD is a trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective owners.
Logic block diagram
Selection guide
-250
-225
-200
-166
Units
Minimum cycle time
4
4.4
5
6
ns
Maximum clock frequency
250
225
200
166
MHz
Maximum pipelined clock access time
2.6
2.8
3.0
3.4
ns
Maximum operating current
450
425
400
350
mA
Maximum standby current
160
150
130
120
mA
Maximum CMOS standby current (DC)
70
mA
Q0
Q1
512K × 32/36
Memory
array
Burst logic
CLK
CLR
CE
Address
DQ
CE
CLK
DQd
CLK
DQ
Byte write
registers
register
DQc
CLK
DQ
Byte write
registers
DQb
CLK
DQ
Byte write
registers
DQa
CLK
DQ
Byte write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers
Input
registers
Power
down
DQ[a:d]
4
36/32
19
17
19
19
GWE
BWE
BWd
ADV
ADSC
ADSP
CLK
CE0
CE1
CE2
BWc
BWb
BWa
OE
ZZ
LBO
OE
FT
CLK
36/32
A[18:0]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33512PFS36A-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFS36A-133TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFS36A-133TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFS36A-133TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFS36A-166TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
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