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參數(shù)資料
| 型號(hào)： | AS91L1006E10F100CF |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Ceramic Conformally Coated / Radial 'Standard & High Voltage Golden Max'; Capacitance [nom]: 36pF; Working Voltage (Vdc)[max]: 500V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic, Conformally Coated; Temperature Coefficient: C0G (NP0); Lead Style: Radial Leaded; Lead Dimensions: 0.100" Lead Spacing; Body Dimensions: 0.150" x 0.210" x 0.130"; Container: Tape & Reel; Qty per Container: 2500 |
| 中文描述： | 該AS91L1006BU是一個(gè)6口的JTAG網(wǎng)關(guān) |
| 文件頁(yè)數(shù)： | 7/28頁(yè) |
| 文件大小： | 415K |
| 代理商： | AS91L1006E10F100CF |
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July 2004
AS91L1006BU
SELF_TEST Register
The AS91L1006BU device supports a
single output pin that can be controlled via the
IEEE1149.1 interface. When the instruction is
loaded into the AS91L1006BU instruction register,
a single bit data register is connected which is
always reset to logic zero when the TAP state
machine enters Capture-DR. This will cause the
SELF_TEST pin to pulse low for one cycle of TCK,
during the Update-DR phase. This low going pulse
can be used to initiate self-tests on PCB’s in a rack
via the JTAG interface.
LSP_ASYNC_RST Register
The AS91L1006BU device supports async
reset tests on the devices connected to the LSPs.
The standard method of performing these tests by
utilizing the primary TRST pin cannot be used as it
will cause the AS91L1006BU to deselect and its
internal registers to be reset. In order to enable
async reset tests on LSPs, the test tool should
instruct the device to toggle the LSP reset pins
while maintaining the set up information in the
AS91L1006BU. When the instruction is loaded
into the AS91L1006BU instruction register, a
single bit data register is connected as the data
register which is always reset to logic zero when
the TAP state machine enters Capture-DR. This
will cause the LSP TRST pins to pulse low for one
TCK cycle, during the Update-DR phase.
AUTOWR Register
This is a 6-bit register that controls the pass-
through of the JTAG Technologies AutoWR
signal to any LSP. The register is reset to all
zeros when entering the Test-Logic-Reset state.
Note: The MCGR is reset to 00 upon receiving TRST or the entering of the
Test-Logic-Reset state
AutoWr
Register
(Bit 2 –
Bit 0)
000
LSP 3
AutoWr
Signal
LSP 2
AutoWr
Signal
LSP 1
AutoWr
Signal
High Z
High Z
High Z
001
High Z
High Z
Active
011
High Z
Active
Active
100
Active
High Z
High Z
101
Active
High Z
Active
110
Active
Active
High Z
111
Active
Active
Active
AutoWr
Register
(Bit 5 – Bit
3)
000
LSP 6
AutoWr
Signal
LSP 5
AutoWr
Signal
LSP 4
AutoWr
Signal
High Z
High Z
High Z
001
High Z
High Z
Active
011
High Z
Active
Active
100
Active
High Z
High Z
101
Active
High Z
Active
110
Active
Active
High Z
111
Active
Active
Active
Table 6 - AUTOWR Register Mapping
www.alsc.com
Alliance Semiconductor
7
2003, 2004 Copyright Alliance Semconductor Corporation. All Rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS91L1006E10F100CG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The AS91L1006BU is a one to 6-port JTAG gateway |
| AS91L1006E10F100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The AS91L1006BU is a one to 6-port JTAG gateway |
| AS91L1006E10F100IF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The AS91L1006BU is a one to 6-port JTAG gateway |
| AS91L1006E10F100IG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The AS91L1006BU is a one to 6-port JTAG gateway |
| AS91L1006E10L100C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The AS91L1006BU is a one to 6-port JTAG gateway |
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