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參數資料
型號: ASM3P2780AF-06OR
廠商: ON Semiconductor
文件頁數: 1/7頁
文件大小: 0K
描述: IC FREQ MOD 4X EMI REDUCT 6TSOP
產品變化通告: Product Obsolescence 24/Jan/2011
標準包裝: 2,500
類型: 頻率調制器,擴展頻譜時鐘發生器
PLL:
輸入: 晶體
輸出: CMOS
電路數: 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無/無
頻率 - 最大: 50MHz
除法器/乘法器: 是/無
電源電壓: 2.375 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: SC-74,SOT-457
供應商設備封裝: 6-TSOP
包裝: 帶卷 (TR)
ASM3P2780A
Peak EMI
Reducing Solution
2010 SCILLC. All rights reserved.
Publication Order Number:
OCTOBER 2010 – Rev. 2
ASM3P2780/D
Features
Generates an EMI optimized clock signal at the
output.
Integrated loop filter components.
Operates with a 3.3 / 2.5V Supply.
Operating current less than 5mA.
CMOS design.
Input frequency range: 30MHz to 50MHz for 2.5V
30MHz to 50MHz for 3.3V
Generates a 1X low EMI spread spectrum clock of
the input frequency.
Frequency deviation: ±0.75% (Typ) @ 46MHz Input
Frequency.
Available in 6L-TSOP (6L-TSOT-23) Package.
Product Description
The ASM3P2780A is a versatile spread spectrum
frequency modulator designed specifically for a wide
range of clock frequencies. The ASM3P2780A reduces
electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of all clock
dependent signals. The ASM3P2780A allows significant
system cost savings by reducing the number of circuit
board layers, ferrite beads and shielding that are
traditionally required to pass EMI regulations.
The ASM3P2780A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented by using a proprietary all digital method.
The ASM3P2780A modulates the output of a single PLL
in order to “spread” the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation.’
Applications
The ASM3P2780A is targeted towards all portable
devices like MP3 players and digital still cameras.
Key Specifications
Description
Specification
Supply voltages
VDD = 3.3V / 2.5V
Cycle-to-Cycle Jitter
±200pS (Typ)
Output Duty Cycle
45/55%
Modulation Rate Equation
FIN/1280
Frequency Deviation
±0.75 (Typ) @ 46MHz
Block Diagram
ModOUT
VSS
XIN / CLKIN
Frequency
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
VCO
Output
Divider
PLL
VDD
PD
Crystal
Oscillator
XOUT
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