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參數資料
| 型號： | AT90CAN64-IL |
| 廠商： | Atmel Corp. |
| 英文描述： | Microcontroller with 32/64k Bytes of ISP Flash and CAN Controller |
| 中文描述： | 微控制器與ISP的閃存和控制器的CAN 32/64k字節 |
| 文件頁數： | 8/16頁 |
| 文件大小： | 560K |
| 代理商： | AT90CAN64-IL |
8
7538AS–CAN–09/05
AT90CAN32/64
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the AT90CAN32/64 as listed on
I/O-Ports paragraph of the complete Datasheet.
2.5.8
Port F (PF7..PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-
metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pull-
up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.
2.5.9
Port G (PG4..PG0)
Port G is a 5-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output
buffers have symmetrical drive characteristics with both high sink and source capability. As
inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are
activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
Port G also serves the functions of various special features of the AT90CAN32/64 as listed on
I/O-Ports paragraph of the complete Datasheet.
2.5.10
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset. The minimum pulse length is given in characteristics. Shorter pulses are not guaranteed
to generate a reset. The I/O ports of the AVR are immediately reset to their initial state even if
the clock is not running. The clock is needed to reset the rest of the AT90CAN32/64.
2.5.11
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.5.12
XTAL2
Output from the inverting Oscillator amplifier.
2.5.13
AVCC
AVCC is the supply voltage pin for the A/D Converter on Port F. It should be externally con-
nected to V
CC
, even if the ADC is not used. If the ADC is used, it should be connected to V
CC
through a low-pass filter.
2.5.14
AREF
This is the analog reference pin for the A/D Converter.
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