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參數(shù)資料
| 型號(hào)： | ATT3020-50T68I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁(yè)數(shù)： | 64/80頁(yè) |
| 文件大小： | 528K |
| 代理商： | ATT3020-50T68I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
64
Lucent Technologies Inc.
Electrical Characteristics
(continued)
Note: The EPROM requirements in this timing diagram are extremely relaxed; EPROM access time can be longer than 4000 ns. EPROM data
output has no hold time requirements.
Figure 37. Master Parallel Mode Switching Characteristics
Notes:
At powerup, V
CC
must rise from 2.0 V to V
CC
minimum in less than 25 ms. If this is not possible, configuration can be delayed by holding
RESET
low until V
CC
has reached 4.0 V. A very long V
CC
rise time of >100 ms, or a nonmonotonically rising V
CC
may require a >1 μs high level on
RESET
, followed by >6 μs low level on
RESET
and D/
P
after V
CC
has reached 4.0 V.
Configuration can be controlled by holding
RESET
low with or until after the
INIT
of all daisy-chain slave mode devices is high.
Table 27. Master Parallel Mode Switching Characteristics
Signal
Description
Symbol
Min
Max
Unit
RCLK
To Address Valid
To Data Setup
To Data Hold
RCLK High
RCLK Low
1
2
3
—
—
T
RAC
T
DRC
T
RCD
T
RCH
T
RCL
0
60
0
600
4.0
200
—
—
—
—
ns
ns
ns
ns
μs
A[15:0]
D[7:0]
RCLK
(OUTPUT)
CCLK
(OUTPUT)
ADDRESS FOR BYTE N + 1
ADDRESS FOR BYTE N
DOUT
(OUTPUT)
BYTE N
D6
D7
T
RAC
T
DRC
T
RCD
CCLK
7 CCLKs
BYTE N – 1
2
3
1
5-3128(F)
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