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參數(shù)資料
| 型號： | ATT3020-70J68I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 8/80頁 |
| 文件大小： | 528K |
| 代理商： | ATT3020-70J68I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
8
Lucent Technologies Inc.
Configurable Logic Block
(continued)
5A. Combinatorial Logic Option 1
generates two functions of four
variables each. One variable, A, must be common to both func-
tions. The second and third variables can be any choice among
B, C, Qx, and Qy. The fourth variable can be either D or E.
5B. Combinatorial Logic Option 2
generates any function of five
variables: A, D, E, and two choices among B, C, Qx, Qy.
5C. Combinatorial Logic Option 3
allows variable E to select
between two functions of four variables: both have common
inputs, A and D, and any choice among B, C, Qx, and Qy for
the remaining two variables. Option 3 can then implement
some functions of six or seven variables.
Figure 5. Combinatorial Logic Diagram
Figure 6 shows a modulo 8 binary counter with parallel
enable. It uses one CLB of each type. The partial func-
tions of six or seven variables are implemented by
using the input variable (.e) to dynamically select
between two functions of four different variables. For
the two functions of four variables each, the indepen-
dent results (F and G) may be used as data inputs to
either flip-flop or logic block output. For the single func-
tion of five variables and merged functions of six or
seven variables, the F and G outputs are identical.
Symmetry of the F and G functions and the flip-flops
allows the interchange of CLB outputs to optimize
routing efficiencies of the networks interconnecting
the logic and IOBs.
Figure 6. C8BCP Macro
A
B
C
D
E
QX
QY
ANY FUNCTION
OF UP TO 4
VARIABLES
F
ANY FUNCTION
OF UP TO 4
VARIABLES
G
QY
QX
A
B
C
D
E
ANY FUNCTION
OF 5
VARIABLES
A
B
C
D
E
QX
QY
F
G
A
B
C
D
QX
QY
A
B
C
D
E
QX
QY
F
G
ANY FUNCTION
OF UP TO 4
VARIABLES
ANY FUNCTION
OF UP TO 4
VARIABLES
M
U
X
5A
5B
5C
5-3104(F)
CLOCK
ENABLE
PARALLEL
ENABLE
CLOCK
TERMINAL
COUNT
D0
Q0
D
Q
Q1
D1
D2
Q2
D
Q
FUNCTION OF 6 VARIABLES
D
Q
FUNCTION OF 5 VARIABLES
DUAL FUNCTION OF
4 VARIABLES
5-3105(F)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ATT3020-70J84I | Field-Programmable Gate Arrays |
| ATT3020-70M132I | Field-Programmable Gate Arrays |
| ATT3020-70M44I | Field-Programmable Gate Arrays |
| ATT3020-70M68I | Field-Programmable Gate Arrays |
| ATT3020-70M84I | Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATT3020-70J84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3020-70M132I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3020-70M44I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3020-70M68 | 制造商:ATandT 功能描述:FPGA, 64 CLBS, 2000 GATES, 84 MHz, PQCC68 |
| ATT3020-70M68I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
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