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參數資料
型號: ATT3020-70M68I
廠商: Electronic Theatre Controls, Inc.
元件分類: FPGA
英文描述: Field-Programmable Gate Arrays
中文描述: 現場可編程門陣列
文件頁數: 32/80頁
文件大小: 528K
代理商: ATT3020-70M68I
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
32
Lucent Technologies Inc.
Power
Power Distribution
Power for the FPGA is distributed through a grid to
achieve high noise immunity and isolation between
logic and I/O. Inside the FPGA, a dedicated V
CC
and
ground ring surrounding the logic array provides power
to the I/O drivers (see Figure 31 below). An indepen-
dent matrix of V
CC
and ground lines supplies the inte-
rior logic of the device. This power distribution grid
provides a stable supply and ground for all internal
logic, provided that the external package power pins
are all connected and appropriately decoupled. Typi-
cally, a 0.1 μF capacitor connected near the V
CC
and
ground pins of the package will provide adequate
decoupling.
Output buffers which drive the specified 4 mA loads
under worst-case conditions may drive 25 to 30 times
this amount under best-case process conditions. Noise
can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in
the same direction. It may also be beneficial to locate
heavily loaded output buffers near the ground pads.
The IOB output buffers have a slew-limited mode which
should be used where output rise and fall times are not
speed critical.
Slew-limited outputs maintain their dc drive capability
but generate less external reflections and internal
noise. More than 32 fast outputs should not be switch-
ing in the same direction simultaneously.
Figure 31. FPGA Power Distribution
V
CC
V
CC
GND
GND
GROUND AND
V
CC
RING FOR
I/O DRIVERS
LOGIC POWER GRID
5-3122(F)
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