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參數資料
| 型號： | ATT3020-70S44I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現場可編程門陣列 |
| 文件頁數： | 27/80頁 |
| 文件大小： | 528K |
| 代理商： | ATT3020-70S44I |
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Lucent Technologies Inc.
27
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Special Configuration Functions
The configuration data includes control over several
special functions in addition to the normal user logic
functions and interconnects:
I
Input thresholds
I
Readback enable
I
DONE pull-up resistor
I
DONE timing
I
RESET timing
I
Oscillator frequency divided by two
Each of these functions is controlled by configuration
data bits which are selected as part of the normal
development system bit stream generation process.
Input Thresholds
Prior to the completion of configuration, all FPGA input
thresholds are TTL compatible. Upon completion of
configuration, the input thresholds become either TTL
or CMOS compatible as programmed. The use of the
TTL threshold option requires some additional supply
current for threshold shifting. The exception is the
threshold of the
PWRDWN
input and direct clocks which
always have a CMOS input. Prior to the completion of
configuration, the user I/O pins each have a high-
impedance pull-up. The configuration program can be
used to enable the IOB pull-up resistors in the opera-
tional mode to act either as an input load or to avoid a
floating input on an otherwise unused pin.
Readback
The contents of an FPGA may be read back if it has
been programmed with a bit stream in which the read-
back option has been enabled. Readback may be used
for verification of configuration and as a method for
determining the state of internal logic nodes. There are
three options in generating the configuration bit stream:
I
Never
will inhibit the readback capability.
I
One-time
will inhibit readback after one readback
has been executed to verify the configuration.
I
On-command
will allow unrestricted use of read-
back.
Readback is accomplished without the use of any of
the user I/O pins; only M0, M1, and CCLK are used.
The initiation of readback is produced by a low-to-high
transition of the M0/RTRIG (read trigger) pin. Once the
readback command has been given, the input CCLK is
driven by external logic to read back each data bit in a
format similar to loading. After two dummy bits, the first
data frame is shifted out on the M1/RDATA (read data)
pin. The logic polarity of the readback data is always
inverted, such that a zero in configuration becomes a
one in readback and vice versa. Each readback frame
has one start bit and one stop bit per frame (configura-
tion writes at least 3 stop bits per frame). All data
frames must be read back to complete the process and
return the mode select and CCLK pins to their normal
functions.
The readback data includes the current state of each
internal logic block storage element, and the state of
the input (.i and .ri) connection pins on each IOB. The
data is imbedded into unused configuration bit posi-
tions during readback. This state information is used by
the FPGA development system in-circuit verifier to pro-
vide visibility into the internal operation of the logic
while the system is operating. To read back a uniform
time sample of all storage elements, it may be neces-
sary to inhibit the system clock.
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