欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數(shù)資料
型號(hào)： ATT3030-50J68I
廠商： Electronic Theatre Controls, Inc.
元件分類： FPGA
英文描述： Field-Programmable Gate Arrays
中文描述： 現(xiàn)場(chǎng)可編程門陣列
文件頁(yè)數(shù)： 5/80頁(yè)
文件大小： 528K
代理商： ATT3030-50J68I
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Lucent Technologies Inc.
5
I/O Block
Each user-configurable I/O block (IOB), shown in
Figure 3, provides an interface between the external
package pin of the device and the internal user logic.
Each IOB includes both registered and direct input
paths and a programmable 3-state output buffer which
may be driven by a registered or direct output signal.
Configuration options allow each IOB an inversion, a
controlled slew rate, and a high-impedance pull-up.
Each input circuit also provides input clamping diodes
to provide electrostatic protection and circuits to inhibit
latch-up produced by input currents.
The input buffer portion of each IOB provides threshold
detection to translate external signals applied to the
package pin to internal logic levels. The global input-
buffer threshold of the IOB can be programmed to be
compatible with either TTL or CMOS levels. The buff-
ered input signal drives the data input of a storage
element which may be configured as a positive-edge
triggered D flip-flop or a low-level transparent latch. The
sense of the clock can be inverted (negative edge/high
transparent) as long as all IOBs on the same clock net
use the same clock sense. Clock/load signals (IOB pins
.ik and .ok) can be selected from either of two die edge
metal lines. I/O storage elements are reset during con-
figuration or by the active-low chip
RESET
input. Both
direct input (from IOB pin .i) and registered input (from
IOB pin .q) signals are available for interconnect.
Figure 3. Input/Output Block
5-3102(F)
OUT
INVERT
3-STATE
INVERT
OUTPUT
SELECT
SLEW
RATE
PASSIVE
PULL UP
PROGRAM-CONTROLLED MEMORY CELLS
V
CC
OUTPUT
BUFFER
FLIP-
FLOP
D
Q
R
TTL OR
CMOS
INPUT
THRESHOLD
FLIP-
FLOP
OR
LATCH
Q
D
R
.lk
.t
= PROGRAMMABLE INTERCONNECTION POINT OR PIP
CK2
(GLOBAL RESET)
I/O PAD
.o
.i
.q
3-STATE
OUT
DIRECT IN
REGISTERED IN
CK1
PROGRAM-
CONTROLLED
MULTIPLEXER
OUTPUT ENABLE
.ok
相關(guān)PDF資料
PDF描述
ATT3030-50J84I Field-Programmable Gate Arrays
ATT3030-50M132I Field-Programmable Gate Arrays
ATT3030-50M44I Field-Programmable Gate Arrays
ATT3030-50M68I Field-Programmable Gate Arrays
ATT3030-50M84I Field-Programmable Gate Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ATT3030-50J84I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays
ATT3030-50M132I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays
ATT3030-50M44I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays
ATT3030-50M68I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays
ATT3030-50M84I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*
主站蜘蛛池模板： 西宁市| 铜梁县| 凯里市| 阳新县| 榆社县| 阿克陶县| 武安市| 娄烦县| 岗巴县| 岳阳市| 灵璧县| 吐鲁番市| 江油市| 庆安县| 资阳市| 嵊州市| 凤庆县| 建宁县| 宁南县| 循化| 新建县| 佛冈县| 万源市| 尖扎县| 维西| 石景山区| 鹰潭市| 石楼县| 陵水| 衡水市| 文水县| 察雅县| 麦盖提县| 湟中县| 邵武市| 彩票| 光山县| 新巴尔虎左旗| 三原县| 衡南县| 安丘市|