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參數資料
| 型號： | ATT3030-70H84I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現場可編程門陣列 |
| 文件頁數： | 16/80頁 |
| 文件大小： | 528K |
| 代理商： | ATT3030-70H84I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
16
Lucent Technologies Inc.
Programmable Interconnect
(continued)
Crystal Oscillator
Figure 16 shows the location of an internal high-speed
inverting amplifier which may be used to implement an
on-chip crystal oscillator. It is associated with the auxil-
iary buffer in the lower right corner of the die. When the
oscillator is configured and connected as a signal
source, two special user IOBs are also configured to
connect the oscillator amplifier with external crystal
oscillator components as shown in Figure 17. A divide-
by-two option is available to ensure symmetry. The
oscillator circuit becomes active before configuration is
complete in order to allow the oscillator to stabilize.
Actual internal connection is delayed until completion
of configuration. In Figure 17, the feedback resistor,
R1, between output and input biases the amplifier at
threshold. The value should be as large as is practical
to minimize loading of the crystal. The inversion of the
amplifier, together with the R-C networks and an AT cut
series resonant crystal, produces the 360° phase shift
of the Pierce oscillator. A series resistor, R2, may be
included to add to the amplifier output impedance when
needed for phase shift control or crystal resistance
matching, or to limit the amplifier input swing to control
clipping at large amplitudes. Excess feedback voltage
may be corrected by the ratio of C2/C1. The amplifier is
designed to be used from 1 MHz to one-half the speci-
fied CLB toggle frequency. Use at frequencies below
1 MHz may require individual characterization with
respect to a series resistance. Crystal oscillators above
20 MHz generally require a crystal which operates in a
third overtone mode, where the fundamental frequency
must be suppressed by an inductor across C2. When
the oscillator inverter is not used, these IOBs and their
package pins are available for general user I/O.
Suggested component values:
R1—0.5 M
to 1 M
R2—0 k
to 1 k
(may be required for low frequency, phase shift, and/or compensation level for Crystal Q)
C1, C2—10 pF to 40 pF
Y1—1 MHz to 20 MHz AT cut series resonant
Figure 17. Crystal Oscillator Inverter
Pin
44-Pin
PLCC
68-Pin
PLCC
84-Pin
PLCC
100-Pin
132-Pin
PPGA
144-Pin
TQFP
160-Pin
QFP
175-Pin
PPGA
208-Pin
SQFP
QFP
TQFP
XTAL1 (OUT)
XTAL2 (IN)
30
26
47
43
57
53
82
76
79
73
P13
M13
75
69
82
76
T14
P15
110
100
R1
R2
C2
C1
XTAL1 (OUT)
XTAL2
(IN)
ALTERNATE
CLOCK BUFFER
INTERNAL
EXTERNAL
D
Q
Y1
L
THIRD
OVERTONE
ONLY
5-3109(F)
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| ATT3030-70J68I | Field-Programmable Gate Arrays |
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| ATT3030-70J100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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| ATT3030-70J132I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3030-70J44I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3030-70J68I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
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