- 您現在的位置：買賣IC網 > PDF目錄379697 > ATT3042-100S44I (Electronic Theatre Controls, Inc.) Field-Programmable Gate Arrays PDF資料下載
參數資料
| 型號： | ATT3042-100S44I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現場可編程門陣列 |
| 文件頁數： | 36/80頁 |
| 文件大小： | 528K |
| 代理商： | ATT3042-100S44I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
36
Lucent Technologies Inc.
RCLK
During master parallel mode configuration,
RCLK
represents a read of an external dynamic
memory device (normally not used).
RDY/
BUSY
During peripheral parallel mode configuration, this pin indicates when the chip is ready for
another byte of data to be written to it. After configuration is complete, this pin becomes a user-
programmed I/O pin.
D[7:0]
This set of eight pins represents the parallel configuration byte for the parallel master and
peripheral modes. After configuration is complete, they are user-programmed I/O pins.
A[15:0]
This set of 16 pins presents an address output for a configuration EPROM during master parallel
mode. After configuration is complete, they are user-programmed I/O pins.
DIN
This user I/O pin is used as serial data input during slave or master serial configuration. This pin
is data zero input in master or peripheral configuration mode.
DOUT
This user I/O pin is used during configuration to output serial configuration data for daisy-
chained slaves’ data in.
TCLKIN
This is a direct CMOS level input to the global clock buffer.
I/O
Input/Output (Unrestricted)
. May be programmed by the user to be input and/or output pin
following configuration. Some of these pins present a high-impedance pull-up (see next page) or
perform other functions before configuration is complete (see above).
Pin Information
(continued)
Table 5. I/O Pins with Special Functions
(continued)
Symbol
Name/Description
相關PDF資料 |
PDF描述 |
|---|---|
| ATT3042-100S68I | Field-Programmable Gate Arrays |
| ATT3042-100S84I | Field-Programmable Gate Arrays |
| ATT3042-100T132I | Field-Programmable Gate Arrays |
| ATT3042-100T44I | Field-Programmable Gate Arrays |
| ATT3042-100T68I | Field-Programmable Gate Arrays |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ATT3042-100S68I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3042-100S84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3042-100T100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| ATT3042-100T132I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3042-100T144 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
發布緊急采購，3分鐘左右您將得到回復。