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參數(shù)資料
| 型號： | ATT3042-100S68I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 24/80頁 |
| 文件大小： | 528K |
| 代理商： | ATT3042-100S68I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
24
Lucent Technologies Inc.
Configuration Modes
(continued)
Peripheral Mode
Peripheral mode provides a simplified interface through which the device may be loaded byte-wide, as a processor
peripheral. Figure 23 shows the peripheral mode connections. Processor write cycles are decoded from the com-
mon assertion of the active-low write strobe (
WS
), and two active-low and one active-high chip selects (
CS0
,
CS1
,
CS2). If all of these signals are not available, the unused inputs should be driven to their respective active levels.
The FPGA will accept 1 byte of configuration data on the D[7:0] inputs for each selected processor write cycle.
Each byte of data is loaded into a buffer register. The FPGA generates a CCLK from the internal timing generator
and serializes the parallel input data for internal framing or for succeeding slaves on data out (DOUT). An output
HIGH on READY/
BUSY
pin indicates the completion of loading for each byte when the input register is ready for a
new byte. As with master modes, peripheral mode may also be used as a lead device for a daisy-chain of slave
devices.
Figure 23. Peripheral Mode
REPROGRAM
+5 V
ADDRESS
BUS
CONTROL
SIGNALS
ADDRESS
DECODE
LOGIC
8
GENERAL-
PURPOSE
USER I/O
OTHER
I/O PINS
LDC
HDC
M2
DOUT
CCLK
CS0
D[7:0]
CS1
CS2
WS
RDY/BUSY
INIT
D/P
RESET
D[7:0]
M0
M1
PWRDWN
*
*
+5 V
DATA
BUS
5 k
OC
5-3114(F)
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