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參數(shù)資料
| 型號： | ATT3042-100S84I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 20/80頁 |
| 文件大小： | 528K |
| 代理商： | ATT3042-100S84I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
20
Lucent Technologies Inc.
Configuration
(continued)
Note: The length count produced by the bit stream generation program = [(40-bit preamble + sum of program data + 1 per daisy-chain device)
rounded up to a multiple of 8] – (2
≤
K
≤
4), where K is a function of DONE and
RESET
timing selected. An additional 8 is added if the
roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached.
* The configuration data consists of a composite 40-bit preamble/length count, followed by one or more concatenated FPGA programs,
separated by 4-bit postambles. An additional final postamble bit is added for each slave device, and the result rounded up to byte boundary.
The length count is two less than the number of resulting bits. Timing of the assertion of DONE and termination of the internal RESET may
each be programmed to occur one cycle before or after the I/O outputs become active.
Figure 20. FPGA Configuration and Start-Up
Table 3. ATT3000 Device Configuration Data
Device
ATT3020
ATT3030
ATT3042
ATT3064
ATT3090
Gates
CLBs
(row x column)
IOBs
Flip-flops
Bits-per-frame
(with 1 start/3 stop)
Frames
Program Data =
Bits
*
Frames + 4
(excludes header)
PROM Size (bits) =
Program Data
+ 40-bit Headers
1500
64
(8 x 8)
64
256
75
2000
100
(10 x 10)
80
360
92
3000
144
(12 x 12)
96
480
108
4500
224
(16 x 14)
120
688
140
6000
320
(20 x 16)
144
928
172
197
14779
241
22176
285
30784
329
46064
373
64160
14819
22216
30824
46104
64200
PREAMBLE
LENGTH COUNT
12
24
75
STOP
DATA FRAME
START
START
4
3
LAST FRAME
4
POSTAMBLE
3
STOP
LENGTH COUNT*
WEAK PULL-UP
PROG
INTERNAL RESET
I/O ACTIVE
DONE
DOUT LEAD DEVICE
HIGH
1/2 CLOCK CYCLE
DELAY FROM DATA INPUT
DATA
3
5-3111(F)
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