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參數資料
| 型號： | ATT3042-50M84I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現場可編程門陣列 |
| 文件頁數： | 5/80頁 |
| 文件大小： | 528K |
| 代理商： | ATT3042-50M84I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Lucent Technologies Inc.
5
I/O Block
Each user-configurable I/O block (IOB), shown in
Figure 3, provides an interface between the external
package pin of the device and the internal user logic.
Each IOB includes both registered and direct input
paths and a programmable 3-state output buffer which
may be driven by a registered or direct output signal.
Configuration options allow each IOB an inversion, a
controlled slew rate, and a high-impedance pull-up.
Each input circuit also provides input clamping diodes
to provide electrostatic protection and circuits to inhibit
latch-up produced by input currents.
The input buffer portion of each IOB provides threshold
detection to translate external signals applied to the
package pin to internal logic levels. The global input-
buffer threshold of the IOB can be programmed to be
compatible with either TTL or CMOS levels. The buff-
ered input signal drives the data input of a storage
element which may be configured as a positive-edge
triggered D flip-flop or a low-level transparent latch. The
sense of the clock can be inverted (negative edge/high
transparent) as long as all IOBs on the same clock net
use the same clock sense. Clock/load signals (IOB pins
.ik and .ok) can be selected from either of two die edge
metal lines. I/O storage elements are reset during con-
figuration or by the active-low chip
RESET
input. Both
direct input (from IOB pin .i) and registered input (from
IOB pin .q) signals are available for interconnect.
Figure 3. Input/Output Block
5-3102(F)
OUT
INVERT
3-STATE
INVERT
OUTPUT
SELECT
SLEW
RATE
PASSIVE
PULL UP
PROGRAM-CONTROLLED MEMORY CELLS
V
CC
OUTPUT
BUFFER
FLIP-
FLOP
D
Q
R
TTL OR
CMOS
INPUT
THRESHOLD
FLIP-
FLOP
OR
LATCH
Q
D
R
.lk
.t
= PROGRAMMABLE INTERCONNECTION POINT OR PIP
CK2
(GLOBAL RESET)
I/O PAD
.o
.i
.q
3-STATE
OUT
DIRECT IN
REGISTERED IN
CK1
PROGRAM-
CONTROLLED
MULTIPLEXER
OUTPUT ENABLE
.ok
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| ATT3042-50S132I | Field-Programmable Gate Arrays |
| ATT3042-50S44I | Field-Programmable Gate Arrays |
| ATT3042-50S68I | Field-Programmable Gate Arrays |
| ATT3042-50S84I | Field-Programmable Gate Arrays |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ATT3042-50N100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| ATT3042-50R132M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| ATT3042-50R84M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| ATT3042-50S132I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3042-50S44I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
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